W83627EHG Nuvoton Technology Corporation of America, W83627EHG Datasheet - Page 154

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W83627EHG

Manufacturer Part Number
W83627EHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheets

Specifications of W83627EHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base address + 4)) for how the settings correspond to individual data rates.
In the PS/2 Model 30 mode, the bit definitions are as follows:
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit disables the precompensation function. It can be set by the software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base address + 4)) for how the settings correspond to individual data rates.
x
7
X
7
x
6
X
6
x
5
5
X
x
X
4
4
X: Reserved
W83627EHF/EF, W83627EHG/EG
X
3
x
3
-143-
X: Reserved
2
x
2
1
1
0
0
DRATE0
DRATE1
NOPREC
Publication Release Date: April 7, 2009
DRATE0
DRATE1
Version 1.94

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