W83627EHG Nuvoton Technology Corporation of America, W83627EHG Datasheet
W83627EHG
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W83627EHG Summary of contents
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... W83627EHF/EF W83627EHG/EG WINBOND LPC I/O Date : November/16/2006 Revision :1.3 ...
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... N/A First published preliminary version. 0.51 N/A Correct typo at 5.11. 1. Correct DC CHARACTERISTICS description 0.52 N/A 2. Update Demo Circuit 3. Add Pb-free part no:W83627EHG 0.6 N/A Add SMART FAN 0.61 N/A Update application circuit Add new part W83627EF and 0.62 N/A W83627EG. ...
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... Temperature Measurement Machine.........................................................................................27 6.4 FAN Speed Count and FAN Speed Control.......................................................................... 28 6.4.1 Fan speed count........................................................................................................................28 6.4.2 Fan speed control......................................................................................................................29 6.5 Smart Fan Control................................................................................................................. 30 6.5.1 Thermal Cruise mode ................................................................................................................30 6.5.2 Fan Speed Cruise mode............................................................................................................32 6.5.3 Manual Control Mode ................................................................................................................32 6.5.4 Smart Fan III Mode ....................................................................................................................37 W83627EHF/EF, W83627EHG/ ...
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... Configuration Register - Index 40h (Bank 0).............................................................................61 6.8.33 Interrupt Status Register 1 - Index 41h (Bank 0) ......................................................................62 6.8.34 Interrupt Status Register 2 - Index 42h (Bank 0) ......................................................................62 6.8.35 SMI# Mask Register 1 - Index 43h (Bank 0) .............................................................................63 W83627EHF/EF, W83627EHG/EG Publication Release Date: Nov. 2006 - III - Revision 1.3 ...
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... AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) ...............84 6.8.78 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) ................84 6.8.79 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) ....84 6.8.80 AUXTIN Temperature Sensor Over-temperature(Low Byte) Register - Index 56h (Bank 2)......85 W83627EHF/EF, W83627EHG/ ...
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... SPECIFICATIONS ........................................................................................................................ 123 8.1 Absolute Maximum Ratings ................................................................................................ 123 8.2 DC CHARACTERISTICS .................................................................................................... 123 8.3 AC CHARACTERISTICS .................................................................................................... 131 8.3.1 Power On / Off Timing .............................................................................................................131 8.3.2 AC Power Failure Resume Timing ..........................................................................................132 9. HOW TO READ THE TOP MARKING.......................................................................................... 136 10. PACKAGE SPECIFICATION ........................................................................................................ 137 W83627EHF/EF, W83627EHG/EG Publication Release Date: Nov. 2006 - V - Revision 1.3 ...
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... Special care might be applied during layout stage or the IC will fail even though its intended function is workable. W83627EHF/EF, W83627EHG/EG Each UART includes a 16-byte send/receive FIFO ” functions. Smart Fan can make system more stable and © ...
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... Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI compatible • Fully programmable serial-interface characteristics: --- 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1 stop bits generation • Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation W83627EHF/EF, W83627EHG/ ...
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... Fast Gate A20 and Hardware Keyboard Reset • 8 Bit Timer/ Counter • Support binary and BCD arithmetic • 6 MHz, 8 MHz, 12 MHz MHz operating frequency Serial Flash ROM Interface • Support bits flash ROM W83627EHF/EF, W83627EHG/EG Publication Release Date: Nov. 2006 - 3 - Revision 1.3 ...
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... Programmable hysteresis and setting points for all monitored items • Over temperature indicate output • Issue SMI#, OVT# to activate system protection • Winbond Hardware DoctorTM Support • 6 VID inputs / outputs • Provide I2C interface to read/write registers Package • 128-pin PQFP W83627EHF/EF, W83627EHG/EG “Thermal CruiseTM” and “Speed - 4 - ...
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... BLOCK DIAGRAM LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Hardware monitor channel and Vref Keyboard/Mouse data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC Game Port URA, B MIDI GPIO PRT HM ACPI KBC W83627EHF/EHG - 5 - Floppy drive ...
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... LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Keyboard/Mouse data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC Game Port URA, B MIDI IR GPIO PRT KBC ACPI W83627EF/ Floppy drive interface signals Serial port A, B interface signals ...
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... AGND 117 BEEP#/(SO) 118 GP21/CPUFANIN1/MSI 119 GP20/CPUFANOUT1/MSO 120 GP17/GPSA2 121 GP16/GPSB2 122 GP15/GPY1 123 GP14/GPY2 124 GP13/GPX2 125 GP12/GPX1 126 GP11/GPSB1 127 GP10/GPSA1 128 W83627EHF/EF, W83627EHG/EG W83627EHF/EHG - GP37/(SUSC#) 63 KDAT/GP26 62 KCLK/GP27 61 3VSB 60 KBRST 59 GA20M 58 (SI)/AUXFANIN1 57 RIA#/GP60 56 DCDA#/GP61 55 VSS 54 ...
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... NC 116 VSS 117 SO 118 GP21/MSI 119 GP20/MSO 120 GP17/GPSA2 121 GP16/GPSB2 122 GP15/GPY1 123 GP14/GPY2 124 GP13/GPX2 125 GP12/GPX1 126 GP11/GPSB1 127 GP10/GPSA1 128 W83627EHF/EF, W83627EHG/ GP37/(SUSC#) 63 KDAT/GP26 62 KCLK/GP27 61 3VSB 60 KBRST 59 GA20M RIA#/GP60 56 DCDA#/GP61 55 VSS 54 SOUTA/GP62(PENKBC) 53 SINA/GP63 52 ...
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... IN LFRAME LRESET W83627EHF/EF, W83627EHG/EG FUNCTION System clock input, which is selective by the register according to the input frequency either 24MHz or 48MHz. Default is 48MHz. Generated PME event. PCI clock 33 MHz input. Encoded DMA Request signal. Serial IRQ Input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral ...
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... Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin can be pulled up internally KΩ( IN DSKCHG# 17 csu ±50%) . The resistor also can be disabled/enabled by bit 7 of LD0-CRF0 (FIPURDWN). Default is disabled. W83627EHF/EF, W83627EHG/EG FUNCTION - 10 - ...
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... OUT / I/O PD0 42 12ts W83627EHF/EF, W83627EHG/EG PRINTER MODE: An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper ...
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... DSRA I/OD GP66 12t W83627EHF/EF, W83627EHG/EG FUNCTION PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode ...
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... SINB IRRX I/OD GP43*** W83627EHF/EF, W83627EHG/EG Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General purpose I/O port 4 bit 6. UART A Request To Send. An active low signal informs the 8 modem or data set that the controller is ready to send data. ...
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... I/OD GP40* 1 Note. The * sign see 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function W83627EHF/EF, W83627EHG/EG UART A Serial Output used to transmit serial data out to the 8 communication link. During power on reset, this pin is pulled down internally(20K ± 30%)and is defined as PENKBC, which provides the power on value for CR24 bit kΩ ...
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... OUT 118 BEEP I/O AUXFANIN1 12ts W83627EHF/EF, W83627EHG/EG Gate A20 output. This pin is high after system reset. (KBC P21) 12 Keyboard reset. This pin is high after system reset. (KBC P20) 12 Keyboard Clock. 16ts General purpose I/O port 2 bit 7. 16t Keyboard Data. 16ts General purpose I/O port 2 bit 6 ...
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... VID1 109 VID0 110 AUXFANIN1 I W83627EHF/EF, W83627EHG/EG Beep function for hardware monitor. This pin is low after 8 system reset. (for H version only, C version is tri-state) Transfer commands, address or data to Serial Flash connected Serial Flash. CASE OPEN detected. An active low level input from an external device when case is opened. This signal can be ...
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... I/OD GP11** GPX1 I/OD 126 GP12* GPX2 I/OD 125 GP13** W83627EHF/EF, W83627EHG/ +3.3V amplitude fan tachometer input. 12ts 0V to +3.3V amplitude fan tachometer input. (Default) 12ts MIDI serial data input. cs General purpose I/O port 2 bit 1. 12t DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & ...
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... CPUFANOUT1 120 OUT GP20 I/OD Note. The * sign see 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function W83627EHF/EF, W83627EHG/EG I/O Joystick II timer pin. This pin connects to Y positioning variable resistors for the Joystick. (Default) 12cs General purpose I/O port 1 bit 4. ...
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... GPIO port 3 GPIO port 4 GPIO port 5 GPIO port 6 5.10.2 GPIO-1 Interface see 5.8 Game Port W83627EHF/EF, W83627EHG/EG Panel Switch Input. This pin is high active with an internal pull td down resistor. General purpose I/O port 5 bit 6. 12t Panel Switch Output. This signal is used for Wake-Up system ...
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... GP26 I/OD 63 KDAT I/OD GP27 I/OD 62 KCLK I/OD W83627EHF/EF, W83627EHG/EG I/O General purpose I/O port 2 bit 0. 12t DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, 12 CPUFANOUT1 & SYSFANOUT are default DC Mode. MIDI serial data output. 12 General purpose I/O port 2 bit 1. ...
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... PSON GP54 I/OD 12t 71 PWROK OD 12 W83627EHF/EF, W83627EHG/EG General purpose I/O port 3 bit 0. General purpose I/O port 3 bit 1 General purpose I/O port 3 bit 2. Secondary LRESET# output 2. 12 Serial Bus clock. General purpose I/O port 3 bit 3. Secondary LRESET# output 3. 12 Serial bus bi-directional Data. ...
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... AVCC 114 AGND 117 GND 20,55 W83627EHF/EF, W83627EHG/EG General purpose I/O port 5 bit 5. mode) Suspended LED output. (This pin is push-pull output mode) 12 General purpose I/O port 5 bit 6. Panel Switch Input. This pin is high active with an internal pull down resistor. ...
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... The other higher bits of these ports is set by W83627EHF/EHG itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. The register structure is showed as the Figure 6.1 W83627EHF/EF, W83627EHG/EG Publication Release Date: Nov. 2006 - Deschutes CPU thermal ...
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... LPC Bus Port 5h Index Register Port 6h Data Register Figure 6.1 : LPC interface access diagram W83627EHF/EF, W83627EHG/EG Smart Fan Configuration Registers 00h-1Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h-44h Fan Divisor Register I 47h Serial Bus Address 48h ...
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... PC monitoring would most often be connected to power suppliers. The CPU Vcore voltage , battery(pin 74), 3VSB(pin 61), 3VCC(pin 12) , AVCC(pin 114) voltage can directly connected to these analog inputs. The +12V voltage inputs should be reduced a factor with external resistors obtain the input range. As Figure 6.2 shows. W83627EHF/EF, W83627EHG/ ...
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... ADC. Both of pin 12 and pin 114 are connected to the power supply VCC with +3.3V. There are two functions in these 2 pins with 3.3V. The first function is to supply internal (digital/analog) power in the W83627EHF/EF, W83627EHG/EG AVCC VBAT Power Inputs ...
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... Table 6.1. TEMPERATURE 8-BIT BINARY +125°C 0111,1101 +25°C 0001,1001 +1°C 0000,0001 +0.5°C - +0°C 0000,0000 -0.5°C - -1°C 1111,1111 -25°C 1110,0111 -55°C 1100,1001 W83627EHF/EF, W83627EHG/EG Ω ≅ where VCC is set to 3.3V. Ω + Ω 008 V 8-BIT DIGITAL OUTPUT 8-BIT HEX ...
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... Figure 6.4. Determine the fan counter according to: In other words, the fan speed counter has been read from register Bank0 Index 28h, 29h, 2Ah ,3Fh and Bank5 53h, the fan speed can be evaluated by the following equation. W83627EHF/EF, W83627EHG/EG TM /Pentium III TM VREF ...
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... The analog output can be programmed in the Bank0 Index 01h, Index 03h, Index 11h and Index 61h. The default value is 111111YY,YY is reserved 2 bits, that is default output value is nearly 3.3 V. The expression of output voltage can be represented as follow , Output Voltage (V) W83627EHF/EF, W83627EHG/EG TIME PER COUNTS REVOLUTION 6 ...
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... In other words, If “current temperature” > “High Limit”, increase fan speed; If “current temperature” < “Low Limit”, decrease fan speed; Otherwise, keep the fan speed. Figure 6.6 PWM fan mode and Figure 6.7 DC fan mode illustrate the Thermal Cruise mode W83627EHF/EF, W83627EHG/EG Pin 115 CPUFanOut0 Pin 116 ...
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... One more protection is provided that Fan output will not be decreased the above (3) situation in order to keep the fans running with a minimum speed. By setting Bank0 Index12h.bit3 Fan output will be decreased to the “Stop Output Value” which are defined at Bank0 Index08h, Index09h and Index17h. W83627EHF/EF, W83627EHG/EG Figure 6.6 Figure 6.7 Publication Release Date: Nov. 2006 - 31 - Revision 1 ...
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... BIOS or application software. The programming method must be set fan configuration at bank 0 index 04h,bit5-4 to 1,index 62h bit5 Then table 6.3-1 displayed current temperature and fan output value at Smart Fan I Mode Besides, these tables 6.3-2 and 6.3-3 used to setting thermal mode or speed cruise mode of Smart Fan I mode W83627EHF/EF, W83627EHG/ Figure 6.8 ...
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... CR[05h] Bit0-3 CR[07h] CPUFANOUT0 CR[06h] Bit4-7 CR[14h] AUXFANOUT CR[13h] Bit0-3 CR[62h] CPUFANOUT1 CR[63h] Bit0-3 W83627EHF/EF, W83627EHG/EG REGISTER NAME CPUTIN Temperature Sensor SYSTIN Temperature Sensor AUXTIN Temperature Sensor CPUFANOUT0 Output Value Select SYSFANOUT Output Value Select AUXFANOUT1 Output Value Select CPUFANOUT1 Output Value Select MIN ...
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... Tolerance, Maximum Fan Output and Minimum Fan Output must be set first. If the currently measured temperature is within the (Target Temperature ± Temperature Tolerance), the fan speed remains constant. (2) In the case that currently measured temperature goes beyond (Target Temperature ＋ W83627EHF/EF, W83627EHG/EG KEEP MIN. FAN TOLERANCE OUTPUT VALUE ...
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... Bank0 Index09h when temperature is always below (Target Temperature X － Temperature Tolerance). Set bit fan speed will decrease to 0 after a time period set in Bank0 Index0Dh. W83627EHF/EF, W83627EHG/EG put must be an integer; otherwise, it may lead to register overflow. must be an integer; otherwise, it may lead to register overflow. ...
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... Fan output (DC / PWM) (DC / PWM) Max. Fan Output Max. Fan Output Fan Initial Fan Initial Output Value Output Value Min. Fan Output Min. Fan Output W83627EHF/EF, W83627EHG/EG Setting Setting Setting Tolerance Tolerance Tolerance Tar. + Tol. Tar. + Tol. Tar. + Tol. Figure 6.9 Tolerance ...
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... Temperature 27H Bank2 Current AUX Temperature 50H,51H Current Bank0 CPUFANOUT0 03H Output Value Current Bank0 SYSFANOUT 01H Output Value W83627EHF/EF, W83627EHG/EG Tolerance Tolerance Tar Tar Tar 2 Tar 2 Tar 3 Tar 3 Tar 1 Tar 1 Figure 6.11 REGISTER NAME CPUTIN Temperature Read only Sensor SYSTIN Temperature ...
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... Status Register. (Figure 6.13 ) High limit Low limit SMI# * *Interrupt Reset when Interrupt Status Registers are read Figure 6.12 W83627EHF/EF, W83627EHG/EG STOP VALUE TOLERANCE (MIN. FAN OUTPUT) CR[07h] bit 4-7 CR[09h] CR[62h] bit 0-3 ...
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... T OI SMI *Interrupt Reset when Interrupt Status Registers are read Figure 6.14 W83627EHF/EF, W83627EHG/ then reset, if the temperature remains above the O and not reset, the interrupts will not occur again. The interrupts O will set temperature sensor 1 SMI# to the Interrupt Mode. The O ...
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... HYST HYST SMI Figure 6.17 W83627EHF/EF, W83627EHG/EG * Figure 6.16 causes an interrupt and this interrupt will be reset by reading all the O , the interrupt will occur again when the next conversion has HYST causes an interrupt and then temperature going below ...
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... T T HYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) W83627EHF/EF, W83627EHG/EG causes the OVT# output activated until the temperature is less than O causes the OVT# output activated indefinitely until reset by reading O O will also cause the OVT# activated indefinitely until reset by HYST , the OVT# will not be activated again ...
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... Bit 7 Bit 6 Reserved (Power On default 0) A6 6.8.2 Data Port (Port x6h) Data Port: Power on Default Value Attribute: Size: 7 Bit 7-0: Data to be read from written to RAM and Register. W83627EHF/EF, W83627EHG/EG Port x5h 00h Bit 6:0 Read/write , Bit 7: Reserved 8 bits Bit 5 Bit 4 ...
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... Bit 6-0: SYSFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider PWM output frequency the formula is W83627EHF/EF, W83627EHG/EG 00h 04h Read/Write 8 bits ...
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... Write 00h, SYSFANOUT is always logical Low which means duty cycle is 0%. Note. XXh: PWM Duty Cycle output percentage is (XX/256*100%) during one cycle. (2)If SYSFANOUT be programmed as DC Voltage output (Bank0 Index 04h.bit0 is 1) Bit 7-2: SYSFANOUT voltage control. Bit 1-0: Reserved. AVCC OUTPUT Voltage = W83627EHF/EF, W83627EHG/EG 01h FFh Read/Write 8 bits ...
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... If AVCC= 3.3V , output voltage table is BIT 7 BIT 6 BIT 5 BIT 4 BIT W83627EHF/EF, W83627EHG/EG OUTPUT BIT 2 BIT 7 BIT 6 BIT 5 VOLTAGE OUTPUT BIT 4 BIT 3 BIT 2 VOLTAGE 2.17 ...
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... The register is meaningful when CPUFANOUT0 be programmed as PWM output. Bit 7: CPUFANOUT0 PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. W83627EHF/EF, W83627EHG/EG OUTPUT BIT 2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 VOLTAGE 1 1 ...
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... Note. XXh: PWM Duty Cycle output percentage is (XX/256*100%) during one cycle. (2)If CPUFANOUT0 be programmed as DC Voltage output (Bank0 Index 04h.bit1 is 1) Bit 7-2: CPUFANOUT0 voltage control. Bit 1-0: Reserved. OUTPUT Voltage = Note. See the Table 6.4 W83627EHF/EF, W83627EHG/EG Input Clock Pre_Scale 03h FFh ...
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... Set to 1, SYSFANOUT pin voltage output which can provide analog voltage output . (Default 1) 6.8.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h (Bank 0) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/EG 04h 01h Read/Write 8 bits ...
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... Register Location: Power on Default Value: Attribute: Size (1)When at Thermal Cruise mode or Bit 7: Reserved. Bit 6-0: CPUTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: CPUFANIN0 Target Speed. W83627EHF/EF, W83627EHG/ Target Temperature / Target Speed 06h 00h Read/Write 8 bits Target Temperature / Target Speed ...
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... Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimam value, and this is Stop Value. W83627EHF/EF, W83627EHG/EG 07h 00h Read/Write ...
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... SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0) Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, SYSFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. W83627EHF/EF, W83627EHG/EG 09h 01h Read/Write 8 bits CPUFANOUT0 Stop Value ...
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... When at Thermal Cruise mode, this register determines the time of which SYSFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. W83627EHF/EF, W83627EHG/EG 0Bh 01h Read/Write 8 bits 4 ...
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... This register determines the speed of FANOUT decreasing its value in Smart Fan Control mode. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 1 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 4 seconds. W83627EHF/EF, W83627EHG/EG 0Dh 3Ch Read/Write 8 bits ...
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... Attribute: Size The register is meaningful when AUXFANOUT be programmed as PWM output. Bit 7: AUXFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. W83627EHF/EF, W83627EHG/EG 0Fh 0Ah Read/Write 8 bits ...
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... Note. XXh: PWM Duty Cycle output percentage is (XX/256*100%) during one cycle. (2)If AUXFANOUT be programmed as DC Voltage output (Bank0 Index 12h.bit0 is 1) Bit 7-2: AUXFANOUT voltage control. Bit 1-0: Reserved. OUTPUT Voltage = Note. See the Table 6.4 W83627EHF/EF, W83627EHG/EG Input Clock Pre_Scale 11h FFh ...
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... Set 11, reserved and no function. Bit 0: AUXFANOUT output mode selection. Set to 0, AUXFANOUT pin is as PWM output duty cycle so that it can drive a logical high or low signal. Set to 1, AUXFANOUT pin voltage output which can provide analog voltage output. (Default 0) W83627EHF/EF, W83627EHG/EG 12h 00h Read/Write ...
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... Register Location: Power on Default Value: Attribute: Size (1)When at Thermal Cruise mode: Bit 3-0: Tolerance of AUXTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 3-0: Tolerance of AUXFANIN0 Target Speed. W83627EHF/EF, W83627EHG/EG 13h 00h Read/Write 8 bits Target Temperature / Target Speed 14h 00h Read/Write ...
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... AUXFANOUT Start-up Value Register - Index 16h (Bank 0) Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. W83627EHF/EF, W83627EHG/EG 15h 01h Read/Write 8 bits AUXFANOUT Stop Value ...
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... Bit 6: Set to 1, disable temperature sensor SYSTIN over-temperature (OVT#) output. Set to 0, enable the SYSTIN OVT# output. Bit 5: Reserved. Bit 4: SYSTIN OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 3-1: Reserved. Bit 0: Reserved. W83627EHF/EF, W83627EHG/EG 17h 3Ch Read/Write 8 bits 4 3 ...
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... VIN0 High Limit 2Eh VIN0 Low Limit 2Fh AVCC High Limit 30h AVCC Low Limit 31h 3VCC High Limit 32h 3VCC Low Limit 33h VIN1 High Limit 34h VIN1 Low Limit 35h VIN2 High Limit 36h VIN2 Low Limit W83627EHF/EF, W83627EHG/EG DESCRIPTION - 60 - ...
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... Configuration Register - Index 40h (Bank 0) Register Location: Power on Default Value: Attribute: Size: 8 bits Bit 7: A one restores power on default value to some registers. This bit clears itself since the power on default is zero. Bit 6: Reserved Bit 5: Reserved W83627EHF/EF, W83627EHG/EG DESCRIPTION 40h 03h Read/Write START SMI#Enable Reserved ...
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... Bit 1: A one indicates a High or Low limit of VIN0 has been exceeded. Bit 0: A one indicates a High or Low limit of CPUVCORE has been exceeded. 6.8.34 Interrupt Status Register 2 - Index 42h (Bank 0) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/EG 41h 00h Read Only 8 bits 6 5 ...
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... Bit 1: A one indicates a High or Low limit of VIN3 has been exceeded. Bit 0: A one indicates a High or Low limit of VIN1 has been exceeded. 6.8.35 SMI# Mask Register 1 - Index 43h (Bank 0) Register Location: Power on Default Value: Attribute: Size: 7 Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. W83627EHF/EF, W83627EHG/ 43h ...
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... Bit 7: CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit won’t be self cleared, please write 0 after event be cleared. The function is as same as LDA, CR[E6h] bit 5. Bit 6-3: Reserved. Bit 2-0: A one disables the corresponding interrupt status bit for SMI interrupt. W83627EHF/EF, W83627EHG/EG 44h FFh Read/Write ...
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... Note : Please refer to Bank0 Index 5Dh , Fan divisor table. 6.8.40 Serial Bus Address Register - Index 48h (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7: Reserved (Read Only). Bit 6-0: Serial Bus address <7:1>. W83627EHF/EF, W83627EHG/EG 47h 55h Read/Write 8 bits ...
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... CPUTIN.(Default) <1:0> AUXTIN. <1:0> – Reserved. 6.8.43 Fan Divisor Register II - Index 4Bh (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7-6: AUXFANIN0 Divisor bit1:0. Note : Please refer to Bank0 Index 5Dh , Fan divisor table. W83627EHF/EF, W83627EHG/EG 4Ah 64h Read/Write 8 bits Reserved ...
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... CPUTIN OVT output through pin OVT#. (default 0) Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. (default 0) Bit 1-0: Reserved. 6.8.45 FAN IN/OUT Control Register - Index 4Dh (Bank 0) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/EG 4Ch 10h Read/Write 8 bits ...
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... Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7: HBACS - High byte access. Set to 1, access Index 4Fh high byte register. Set to 0, access Index 4Fh low byte register. (default 1) Bit 6: Reserved. This bit should be set to 0. W83627EHF/EF, W83627EHG/ 4Eh 80h ...
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... Bit 15-8: Vendor ID High Byte if Index 4Eh.bit7=1. Default 5Ch. Bit 7-0: Vendor ID Low Byte if Index 4Eh.bit7=0. Default A3h. 6.8.48 Winbond Test Register - Index 50h-55h (Bank 0) 6.8.49 BEEP Control Register 1 - Index 56h (Bank 0) Register Location: Power on Default Value: Attribute: Size: 7 W83627EHF/EF, W83627EHG/EG 4Fh <15:0> = 5CA3h Read Only 16 bits VIDH ...
Page 76
... Bit 2: BEEP output control for VIN3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 1: BEEP output control for VIN2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. W83627EHF/EF, W83627EHG/EG 57h 80h Read/Write ...
Page 77
... Pentium II CPU compatible thermal diode. Bit 4: Diode mode selection of temperature SYSTIN if Index 5Dh bit1 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Bit 3-2: AUXFANIN1 Divisor bit 1:0. Bit 1-0: CPUFANIN1 Divisor bit 1:0. W83627EHF/EF, W83627EHG/EG 58h A1h Read Only 8 bits ...
Page 78
... Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. After set this bit from the monitored value will be updated to the VBAT reading value register after one monitor cycle time. Fan divisor table : BIT 2 BIT 1 BIT W83627EHF/EF, W83627EHG/EG 5Dh 00h Read/Write 8 bits EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved SYSFANIN DIV_B2 CPUFANIN0 DIV_B2 AUXFANIN0 DIV_B2 ...
Page 79
... The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider PWM output frequency the formula is 6.8.57 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/EG 60h 04h Read/Write 8 bits Input = ...
Page 80
... Bit7 : Reserved. Bit 6: CPUFANOUT1 output mode selection. Set to 0, CPUFANOUT1 pin is as PWM output duty cycle so that it can drive a logical high or low signal. Set to 1, CPUFANOUT1 pin voltage output which can provide analog voltage output. (Default 1) W83627EHF/EF, W83627EHG/ CPUFANOUT1 Value FANOUT ...
Page 81
... Bit 6-0: Target Temperature of select temperature source. (2)When at Fan Speed Cruise mode: Bit 7-0: CPUFANIN1 Target Speed. 6.8.60 CPUFANOUT1 Stop Value Register - Index 64h (Bank 0) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/EG TM III Mode. TM SMART FAN III mode: 63h ...
Page 82
... When at Thermal Cruise mode, CPUFANOUT1 value will increase from 0 to this register value to provide a minimum value to turn on the fan. 6.8.62 CPUFANOUT1 Stop Time Register - Index 66h (Bank 0) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/ CPUFANOUT1 Stop Value TM SMART FAN ...
Page 83
... III mode, CPUFANOUT0 value will increase to this value. This register should be written a non-zero value that cannot lower than Stop value. 6.8.64 CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/ CPUFANOUT1 Stop Time ...
Page 84
... Stop value. 6.8.66 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0) Register Location: Power on Default Value: Attribute: Size This register determines the value that CPUFANOUT1 in SMART FAN increased to the next speed. W83627EHF/EF, W83627EHG/ 69h FFh Read/Write 8 bits 4 ...
Page 85
... Bit 7-0: Temperature <8:1> of CPUTIN sensor, which is high byte, means 1 6.8.68 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: 51h Attribute: Read Only Size: 8 bits 7 6 Bit 7: Temperature <0> of CPUTIN sensor, which is low byte, means 0.5 Bit 6-0: Reserved. W83627EHF/EF, W83627EHG/ TEMP< ...
Page 86
... Bit 0: Read/Write - When set to 1 the sensor will stop monitor. 6.8.70 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) Register Location: Power on Default Value: Attribute: Size Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. W83627EHF/EF, W83627EHG/EG 52h 00h 8 bits ...
Page 87
... Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.72 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) Register Location: Power on Default Value: Attribute: Size Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. W83627EHF/EF, W83627EHG/EG 54h 00h Read/Write 8 bits ...
Page 88
... Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.74 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2) Register Location: 50h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <8:1> of AUXTIN sensor, which is high byte, means 1 W83627EHF/EF, W83627EHG/EG 56h 00h Read/Write 8 bits ...
Page 89
... Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. W83627EHF/EF, W83627EHG/ ...
Page 90
... Power on Default Value: Attribute: Size: 7 Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.79 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/EG 53h 4Bh Read/Write 8 bits 54h 00h ...
Page 91
... AUXTIN Temperature Sensor Over-temperature(Low Byte) Register - Index 56h (Bank 2) Register Location: Power on Default Value: Attribute: Size: 7 Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.81 Interrupt Status Register 3 - Index 50h (Bank 4) Register Location: Power on Default Value: Attribute: Size W83627EHF/EF, W83627EHG/ 56h 00h Read/Write 8 bits ...
Page 92
... Bit 4: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 3-2: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. W83627EHF/EF, W83627EHG/EG 51h 00h Read/Write ...
Page 93
... Register Location: Power on Default Value: Attribute: Size Bit 7-0: SYSTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. W83627EHF/EF, W83627EHG/EG 53h 00h Read/Write 8 bits ...
Page 94
... Register Location: Power on Default Value: Attribute: Size Bit 7-0: AUXTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. W83627EHF/EF, W83627EHG/EG 55h 00h Read/Write 8 bits ...
Page 95
... Bit 0: CPUVCORE Voltage status. Read 1, the voltage of CPUVCORE is over/under the limit value. Read 0, the voltage of CPUVCORE is in the limit range. 6.8.90 6.8.90 Real Time Hardware Status Register II - Index 5Ah (Bank 4) Register Location: Power on Default Value: Attribute: Size: W83627EHF/EF, W83627EHG/EG 59h 00h Read Only 8 bits 5 4 ...
Page 96
... Real Time Hardware Status Register III - Index 5Bh (Bank 4) Register Location: Power on Default Value: Attribute: Size Bit 7: AUXFANIN1 status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. W83627EHF/EF, W83627EHG/ VIN1_STS TAR4_STS ...
Page 97
... VIN4 Low Limit 5Ah Reserved 5Bh Reserved AUXFANIN1 Fan Count Limit 5Ch Note the number of counts of the internal clock for the Low Limit of the fan speed. 6.8.94 Winbond Test Register - Index 50h-57h (Bank 6) W83627EHF/EF, W83627EHG/EG DESCRIPTION Publication Release Date: Nov. 2006 - Revision 1.3 ...
Page 98
... FDC Power Down. CR 23h. (IPD; Default 00h) BIT READ / WRITE 7~1 Reserved. IPD (Immediate Power Down). When set to 1, whole chip is put into power down mode immediately. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION 88h (higher byte). DESCRIPTION 6Xh (lower byte). X for IC version DESCRIPTION 0: Power down ...
Page 99
... URATRI PRTTRI 2~1 Reserved FDCTRI. W83627EHF/EF, W83627EHG/EG s: value by strapping DESCRIPTION The clock input on pin18 is 24MHz. The clock input on pin18 is 48MHz. (Default) KBC is disabled after hardware reset. KBC is enabled after hardware reset. ROM is disabled after hardware reset. ROM is enabled after hardware reset. ...
Page 100
... IRQ. DSUBLGRQ => (base = 1 register (base address + 4) bit 3 is not effective on selecting IRQ. W83627EHF/EF, W83627EHG/EG s: value by strapping DESCRIPTION Select two FDD mode. Select four FDD mode. Write 87h to location 2E twice. Write 87h to location 4E twice. Enable R/W configuration registers. ...
Page 101
... PIN119~120 function select Bit-2 2 PIN121~128 function select W83627EHF/EF, W83627EHG/EG DESCRIPTION (Default) 8M Enable decoding of BIOS ROM range at 000E xxxxh. Disable decoding of BIOS ROM range at 000E xxxxh. Enable decoding of BIOS ROM range at FFFE xxxxh. Disable decoding of BIOS ROM range at FFFE xxxxh. Parallel Port Mode. ...
Page 102
... Note: The bit will be ignored while CR2A bit-1 is High. 4 Reserved EN_VRM10 Configure bit = The bit is strapping by PIN77 (GP50).--- Pull high to 3VSB. W83627EHF/EF, W83627EHG/EG DESCRIPTION Normal mode. Extend dummy cycle mode. Normal mode. Fast mode interafce) {PIN89, PIN90} set by CR2C[6:5]. {PIN89, PIN90} SDA, SCL ...
Page 103
... PIN70 Select (reset by RSMRST PIN71 Select (reset by RSMRST PIN72 Select (reset by RSMRST PIN73 Select (reset by RSMRST W83627EHF/EF, W83627EHG/EG DESCRIPTION Thermal shutdown function is disabled. Enable thermal shutdown function. Bit-1 Bit-0 PIN82 Reserved 0 0 PIN83 Reserved Others PIN82 IRRX 0 1 PIN83 IRTX Others ...
Page 104
... These two registers select FDC I/O base address <100h : FF8h> 7 bytes boundary. CR 70h. (Default 06h) BIT READ / WRITE 7~4 Reserved. 3 These bits select IRQ resource for FDC. W83627EHF/EF, W83627EHG/EG DESCRIPTION PIN75 RSMRST# PIN75 GPIO51 PIN77 WDTO# PIN77 GPIO50 DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 105
... Media ID1, Media ID0. These bits will be reflected on FDC’s Tape Drive 5 Register bit 7, 6. Density Select. 3 00: Normal. 10: 1 (Forced to logic 1). W83627EHF/EF, W83627EHG/EG DESCRIPTION 001: DMA1. 010: DMA2. DESCRIPTION 1: Drive and Motor select 0 and 1 are swapped. 00: Model 30. 10: Reserved. 0: Burst Mode is enabled 1: Non-Burst Mode ...
Page 106
... Data Rate Table selection (Refer to TABLE A). 4 00: Select regular drives and 2.88 format. 01: 3-mode drive. 2 Reserved. 1 Drive Type selection (Refer to TABLE B). CR F5h. (Default 00h) BIT READ / WRITE 7 Same as FDD0 of CR F5h. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION 10: 2 Meg Tape. DESCRIPTION - 100 - 11: Reserved. ...
Page 107
... TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 TABLE B DTYPE0 DTYPE1 DRVDEN0 (PIN W83627EHF/EF, W83627EHG/EG DATA RATE SELECTED DATA RATE DRATE1 DRATE0 MFM 1 1 1Meg 0 0 500K 0 1 300K 1 0 250K 1 1 1Meg 0 0 500K 0 1 500K 1 0 250K 1 1 1Meg 0 0 500K ...
Page 108
... ECP mode. 2 011: ECP and EPP – 1.9 mode. 100: Printer Mode. 101: EPP – 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP – 1.7 mode. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. DESCRIPTION - 102 - ...
Page 109
... Reserved. 00: UART A clock source is 1.8462 MHz (24 MHz / 13). 01: UART A clock source is 2 MHz (24 MHz / 12). 1 10: UART A clock source is 24 MHz (24 MHz / 1). 11: UART A clock source is 14.769 MHz (24 MHz / 1.625). W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: Nov. 2006 - 103 - ...
Page 110
... Transmission delay 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. 00: UART B clock source is 1.8462 MHz (24 MHz / 13). 01: UART B clock source is 2 MHz (24 MHz / 12). 1 10: UART B clock source is 24 MHz (24 MHz / 1). 11: UART B clock source is 14.769 MHz (24 MHz / 1.625). W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION - 104 - ...
Page 111
... IrDA 100 ASK-IR 101 ASK-IR 110 ASK-IR 111* ASK-IR Note: The notation is normal mode in the IR function . W83627EHF/EF, W83627EHG/EG DESCRIPTION IRTX Tri-state Active pulse 1.6 μS Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & ...
Page 112
... CR 72h. (Default 0Ch) BIT READ / WRITE 7~4 Reserved. 3 These bits select IRQ resource for MINT. (PS/2 Mouse interrupt) CR F0h. (Default83h) BIT READ / WRITE KBC clock rate selection 00: 6MHz 7 01: 8MHz 10: 12MHz 11: 16MHz 5~3 Reserved. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION - 106 - ...
Page 113
... GPIO1 is inactive. CR 60h, 61h. (Default 02h, 01h) BIT READ / WRITE These two registers select Game Port base address <100h : FFFh> 7 byte boundary. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 1: Activate GPIO6. 1: Activate MIDI Port. 1: Activate Game Port. 1: Activate GPIO1. DESCRIPTION Publication Release Date: Nov. 2006 - 107 - Revision 1 ...
Page 114
... CR F2h. (GPIO1 Inversion register; Default 00h) BIT READ / WRITE GPIO1 Inversion register 0: The respective bit and the port value are the same. 7 The respective bit and the port value are inverted. (Both Input & Output ports) W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION - 108 - ...
Page 115
... CR F6h. (GPIO6 Inversion register; Default 00h) BIT READ / WRITE GPIO6 Inversion register 0: The respective bit and the port value are the same. 7 The respective bit and the port value are inverted. (Both Input & Output ports) W83627EHF/EF, W83627EHG/EG DESCRIPTION PLED WDTO# PLED WDTO# PLED WDTO# PLED ...
Page 116
... Second Mode. 1: Minute Mode. Enable the rising edge of KBC reset (P20) to issue time-out event Disable. 1: Enable. Disable / Enable the WDTO# output low pulse to the KBRST# pin (PIN60 Disable. 1: Enable. 0 Reserved. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION 1: Activate WDTO#. DESCRIPTION pulse with 50% duty cycle 110 - ...
Page 117
... Logical Device 9 (GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED) (VSB Power) CR 30h. (Default 00h) BIT READ / WRITE 7~4 Reserved GPIO5 is inactive GPIO4 is inactive GPIO3 is inactive GPIO2 is inactive. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION 1: Activate GPIO5 1: Activate GPIO4. 1: Activate GPIO3. 1: Activate GPIO2. Publication Release Date: Nov. 2006 - 111 - Revision 1.3 ...
Page 118
... READ / WRITE GPIO2 Data register For Output ports, the respective bits can be read/written and produced to pins. 7~0 For Input ports, the respective bits can be read only from pins. Write Read Only accesses will be ignored. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION - 112 - ...
Page 119
... READ / WRITE Select Suspend LED mode. 00: Suspend LED pin is tri-stated. 7 01: Suspend LED pin is driven low. 10: Suspend LED pin outputs 1Hz pulse with 50% duty cycle. 11: Suspend LED pin outputs 5~0 Reserved. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION pulse with 50% duty cycle. 4 Publication Release Date: Nov ...
Page 120
... CR F7h. (GPIO4 multi-function select register; Default 00h) BIT READ / WRITE 0: GPIO47 GPIO47 0: GPIO46 GPIO46 0: GPIO45 GPIO45 0: GPIO44 GPIO44 0: GPIO43 GPIO43 0: GPIO42 GPIO42 0: GPIO41 GPIO41 0: GPIO40 GPIO40 W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION SUSLED WDTO# SUSLED WDTO# SUSLED WDTO# SUSLED WDTO# - 114 - ...
Page 121
... Disable mouse wake-up function via PSOUT#. 1: Enable mouse wake-up function via PSOUT#. MSRKEY => 3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please check out the following table for the detailed. ENMDAT_UP MSRKEY W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION MSXKEY ...
Page 122
... This bit is 0: When power-loss occurs and VSB power is on, indicate that Read Only turn on system power. 4 This bit is 1: When power-loss occurs and VSB power is on, indicate that Read-Clear turn off system power. If E4[ => This bit is always 0. W83627EHF/EF, W83627EHG/EG DESCRIPTION (VSB power) DESCRIPTION (VSB power) DESCRIPTION DESCRIPTION - 116 - ...
Page 123
... Enable the hunting mode for all wake-up events set in CRE0. This bit is cleared when any wake-up events is captured Disable. 1: Enable. 1~0 Reserved. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION issues a low pulse. power loss if SUSB#（Pin 73）is logic high. on the state before power loss. (LRESET#) - 117 - ...
Page 124
... PWROK_DEL Set the delay rising time from PWROK_ST to POWEROK. 2 00: No delay time. 10 PWROK_TRIG => W-Clear Write 1 to re-trigger POWEROK signals from low to high. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION (VSB) (VSB) (VSB) (VSB) 01: Delay 32 ms 11: Delay 250 ms - 118 - This bit won’t be self ...
Page 125
... CRE4[6:5], logic device A. (for SiS & VIA chipsets) 0: Disable. 1: Enable. Select WDTO# reset source Watchdog timer is reset by LRESET#. 1: Watchdog timer is reset by POWEROK 2~1 Reserved. Hardware Monitor RESET source select (VBAT POWEROK 1: LRESET# W83627EHF/EF, W83627EHG/EG DESCRIPTION (VSB) (VSB) (VSB) (VBAT) (VSB) Publication Release Date: Nov. 2006 - 119 - Revision 1.3 ...
Page 126
... PME status of the FDC IRQ event W-Clear Write 1 to clear this status. PME status of the URA IRQ event W-Clear Write 1 to clear this status. PME status of the URB IRQ event W-Clear Write 1 to clear this status. W83627EHF/EF, W83627EHG/EG DESCRIPTION 0: Disable PME. 1: Enable PME. DESCRIPTION - 120 - ...
Page 127
... Enable PME interrupt of the WDTO# event. 0: Disable PME interrupt of the MIDI IRQ event Enable PME interrupt of the MIDI IRQ event. 0: Disable PME interrupt of the RIB event Enable PME interrupt of the RIB event. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: Nov. 2006 - 121 - Revision 1.3 ...
Page 128
... CR F0h. (VID Control register; Default C1h) BIT READ / WRITE VID I/O Control (CRF1[5:0 VID output mode. 1: VID input mode. 6-0 Reserved. CR F1h. (VID Data Register; Default 00h) BIT READ / WRITE 7~6 Reserved. 5 VID[5:0] Data Register. W83627EHF/EF, W83627EHG/EG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION - 122 - ...
Page 129
... TTL level bi-directional pin with 12mA source-sink capability 12t Input Low Voltage V Input High Voltage V Output Low Voltage V Output High Voltage V Input High Leakage I Input Low Leakage I W83627EHF/EF, W83627EHG/EG RATING -0.5 to 6.5 -0 2 +70 -55 to +150 = 0V 5V± 10% tolerance MIN. TYP. ...
Page 130
... Input Low Leakage I I/O - TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability 24ts Input Low Threshold V Voltage Input High Threshold V Voltage Hystersis V Output Low Voltage V Output High Voltage V W83627EHF/EF, W83627EHG/EG MIN. TYP. MAX. 0.8 IL 2.0 IH 0.4 OL 2.4 OH +10 LIH -10 LIL 0 ...
Page 131
... TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink 12ts capability Input Low Threshold Voltage Input High Threshold V Voltage Hystersis V Output Low Voltage V Input High Leakage I W83627EHF/EF, W83627EHG/EG MIN. TYP. MAX. +10 LIH -10 LIL 0.5 0.8 1.1 t- 1.6 2.0 2 ...
Page 132
... CMOS level Schmitt-trigger bi-directional pin and open drain output with 16mA 16 cs sink capability Input Low Threshold V Voltage Input High Threshold V Voltage Hystersis V Output Low Voltage V Input High Leakage I Input Low Leakage I W83627EHF/EF, W83627EHG/EG TYP MIN. MAX -10 LIL V 0.5 0.8 1 1.6 2.0 2 ...
Page 133
... Output pin with 8mA source-sink capability 8 Output Low Voltage Output High Voltage O - Output pin with 12mA source-sink capability 12 Output Low Voltage Output High Voltage O - Output pin with 16mA source-sink capability 16 Output Low Voltage Output High Voltage W83627EHF/EF, W83627EHG/EG TYP MIN. MAX 0.5 0.8 1 1.6 2.0 2.4 ...
Page 134
... Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage IN - TTL level input pin with internal pull down resistor td Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage W83627EHF/EF, W83627EHG/EG TYP MIN. MAX. . 0.4 OL 2.4 OH 0.4 OL ...
Page 135
... CMOS level input pin c Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage IN - CMOS level input pin with internal pull down resistor cd Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage W83627EHF/EF, W83627EHG/EG TYP MIN. MAX 0 2 +10 ...
Page 136
... Hystersis V Input High Leakage Input Low Leakage IN - CMOS level Schmitt-trigger input pin with internal pull up resistor csu Input Low Threshold Voltage Input High Threshold Voltage Hystersis V Input High Leakage Input Low Leakage W83627EHF/EF, W83627EHG/EG TYP MIN. MAX 1.3 1.5 1 +10 ...
Page 137
... AC CHARACTERISTICS 8.3.1 Power On / Off Timing PSON# SUSB# (Intel Chipset) SUSB# (SiS/VIA/Nvidia Chipset) PSOUT# T1 PSIN VSB Typical Timing (Sec) W83627EHF/EF, W83627EHG/ 61m 131 - 21m Over 64m at least Publication Release Date: Nov. 2006 Revision 1.3 ...
Page 138
... VCC PSOUT# PSON# SUSB# RSMRST# VSB ACLOSS 2. CRE4 bit7 = “0” and CRE4 bit[6:5] are selected to “ON” state (“ON” means always turn on or last state is on) VCC PSOUT# PSON# SUSB# RSMRST# VSB ACLOSS W83627EHF/EF, W83627EHG/EG - 132 - ...
Page 139
... VSB ACLOSS 4. CRE4 bit7 = “1” and CRE4 bit[6:5] are selected to “ON” state (“ON” means always turn on or last state is on) VCC PSOUT# PSON# SUSB# RSMRST# VSB ACLOSS W83627EHF/EF, W83627EHG/EG T ≒ 4S Publication Release Date: Nov. 2006 - 133 - Revision 1.3 ...
Page 140
... To prevent that VCC goes down faster than VSB in various ATX Power Supply. W83627EHF/EF,W83627EHG/EG add the “user define mode” option for AC power loss pre-state. BIOS can set the pre-state that is “On” or “Off” state, because the status of AC power resume depends on it ...
Page 141
... System turns off / on when come back from power loss state depend 11: User define the state before power loss.(The last state set at CRE6[4]) CR E6h Power loss Last State Flag. (VBAT OFF W83627EHF/EF, W83627EHG/EG (VBAT) on the state before power loss. - 135 - Publication Release Date: Nov. 2006 Revision 1.3 ...
Page 142
... W83627EF 330G9A282012345UB 1st line: Winbond logo 2nd line: the type number: W83627EHF/EF, W83627EHG/EG (Pb-free package) 3rd line: the tracking code 030A7C282012345UA 330: packages made in '03, week 30 G: assembly house ID; G means GR, A means ASE ... etc. 9: code version; 9 means code 009 A: IC revision ...
Page 143
... PACKAGE SPECIFICATION (128-pin PQFP 102 103 128 See Detail F y Seating Plane W83627EHF/EF, W83627EHG/ Detail F - 137 - Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom A 0.25 0.35 0.45 0.010 0.014 1 A 2.57 2.72 2.87 0.101 0.107 2 b 0.10 0.20 0.30 ...
Page 144
... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83627EHF/EF, W83627EHG/EG Important Notice - 138 - ...