PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 6

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PI7C9X7952AFDE

Manufacturer Part Number
PI7C9X7952AFDE
Description
IC PCIE-TO-UART BRIDGE 128LQFP
Manufacturer
Pericom Semiconductor
Datasheets

Specifications of PI7C9X7952AFDE

Applications
PCIe-to-Uart Bridge
Interface
Advanced Configuration Power Interface (ACPI)
Voltage - Supply
1.8V, 3.3V
Package / Case
128-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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PI7C9X7952AFDE
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7.
8.
September 2009 – Revision 1.3
Pericom Semiconductor
7.1.
7.2.
8.1.
8.2.
8.3.
UART REGISTER DESCRIPTION..................................................................................................42
7.1.1.
7.1.2.
7.1.3.
7.1.4.
7.1.5.
7.1.6.
7.1.7.
7.1.8.
7.1.9.
7.1.10.
7.1.11.
7.1.12.
7.1.13.
7.2.1.
7.2.2.
7.2.3.
7.2.4.
7.2.5.
7.2.6.
7.2.7.
7.2.8.
7.2.9.
7.2.10.
7.2.11.
7.2.12.
7.2.13.
7.2.14.
7.2.15.
7.2.16.
7.2.17.
7.2.18.
7.2.19.
7.2.20.
7.2.21.
7.2.22.
7.2.23.
7.2.24.
7.2.25.
7.2.26.
7.2.27.
7.2.28.
7.2.29.
7.2.30.
7.2.31.
EEPROM INTERFACE .....................................................................................................................61
REGISTERS IN I/O MODE ..........................................................................................................42
R
AUTO MODE EERPOM ACCESS ...............................................................................................61
EEPROM MODE AT RESET ........................................................................................................61
EEPROM SPACE ADDRESS MAP AND DESCRIPTION ..........................................................61
EGISTERS IN
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................43
TRANSMIT HOLDING REGISTER – OFFSET 00h..............................................................43
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................43
INTERRUPT STATUS REGISTER – OFFSET 02h................................................................44
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................44
LINE CONTROL REGISTER – OFFSET 03h .......................................................................45
MODEM CONTROL REGISTER – OFFSET 04h .................................................................45
LINE STATUS REGISTER – OFFSET 05h ............................................................................46
MODEM STATUS REGISTER – OFFSET 06h......................................................................47
SPECIAL FUNCTION REGISTER – OFFSET 07h...............................................................47
DIVISOR LATCH LOW REGISTER – OFFSET 00h, LCR[7] = 1 ........................................48
DIVISOR LATCH HIGH REGISTER – OFFSET 01h, LCR[7] = 1.......................................48
SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[7] = 1 .................................................48
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................50
TRANSMIT HOLDING REGISTER – OFFSET 00h..............................................................51
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................51
INTERRUPT STATUS REGISTER – OFFSET 02h................................................................51
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................52
LINE CONTROL REGISTER – OFFSET 03h .......................................................................52
MODEM CONTROL REGISTER – OFFSET 04h .................................................................53
LINE STATUS REGISTER – OFFSET 05h ............................................................................54
MODEM STATUS REGISTER – OFFSET 06h......................................................................54
SPECIAL FUNCTION REGISTER – OFFSET 07h...............................................................55
DIVISOR LATCH LOW REGISTER – OFFSET 08h .............................................................55
DIVISOR LATCH HIGH REGISTER – OFFSET 09h............................................................55
ENHANCED FUNCTION REGISTER – OFFSET 0Ah.........................................................55
XON SPECIAL CHARACTER 1 – OFFSET 0Bh...................................................................57
XON SPECIAL CHARACTER 2 – OFFSET 0Ch ..................................................................57
XOFF SPECIAL CHARACTER 1 – OFFSET 0Dh ................................................................57
XOFF SPECIAL CHARACTER 2 – OFFSET 0Eh ................................................................57
ADVANCE CONTROL REGISTER – OFFSET 0Fh ..............................................................57
TRANSMIT INTERRUPT TRIGGER LEVEL – OFFSET 10h................................................58
RECEIVE INTERRUPT TRIGGER LEVEL – OFFSET 11h ..................................................58
FLOW CONTROL LOW TRIGGER LEVEL – OFFSET 12h .................................................58
FLOW CONTROL HIGH TRIGGER LEVEL – OFFSET 13h ...............................................58
CLOCK PRESCALE REGISTER – OFFSET 14h..................................................................58
RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[6] = 0..........................................58
LINE STATUS REGISTER COUNTER – OFFSET 15h, SFR[6] = 1 ....................................59
TRANSMIT FIFO DATA COUNTER – OFFSET 16h, SFR[7] = 1 .......................................59
SAMPLE CLOCK REGISTER – OFFSET 16h, SFR[7] = 0 .................................................59
GLOBAL LINE STATUS REGISTER – OFFSET 17h ............................................................59
RECEIVE FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh..............................................60
TRANSMIT FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh ...........................................60
LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh ..................................................60
M
EMORY
09-0087
-M
APPING
M
ODE
Page 6 of 68
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PCI Express® Dual UART
PI7C9X7952
Datasheet

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