PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 34

• Manufacturer Part Number: PI7C9X7952AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7952AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.49. PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h
6.2.50. DEVICE CAPABILITIES REGISTER – OFFSET E4h
6.2.51. DEVICE CONTROL REGISTER – OFFSET E8h
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
19:16
23:20
24
29:25
31:30
BIT
2:0
4:3
5
8:6
11:9
12
13
14
15
17:16
25:18
27:26
31:28
BIT
FUNCTION
Capability Version
Device/Port Type
Slot Implemented
Interrupt Message
Number
Reserved
FUNCTION
Max_Payload_Size
Supported
Phantom Functions
Supported
Extended Tag Field
Supported
Endpoint L0s
Acceptable Latency
Endpoint L1
Acceptable Latency
Attention Button
Present
Attention Indicator
Present
Power Indicator
Present
Role_Base Error
Reporting
Reserved
Captured Slot Power
Limit Value
Captured Slot Power
Limit Scale
Reserved
FUNCTION
09-0087
TYPE
TYPE
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 34 of 68
DESCRIPTION
Read as 0001b to indicate the I/O bridge is compliant to Revision
1.0a of PCI Express Base Specifications.
Indicates the type of Legacy PCI Express Endpoint device.
Reset to 1h.
It is not implemented. Hardwired to 00000b.
Reset to 00b.
It is not implemented. Hardwired to 0b.
DESCRIPTION
Indicates the maximum payload size that the I/O bridge can support
for TLPs. The I/O bridge supports 128 bytes max payload size.
Reset to000b.
It is not implemented. Hardwired to 00b.
It is not implemented. Hardwired to 0b.
Acceptable total latency that an Endpoint can withstand due to the
transition from L0s state to the L0 state.
Reset to 000b.
Acceptable total latency that an Endpoint can withstand due to the
transition from L1 state to the L0 state.
Reset to 000b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
When set, indicated that the device implements the functionality
originally defined in the Error Reporting ECN. The default value
may be changed by auto-loading from EEPROM.
Reset to 1b.
Reset to 00b.
In combination with the Slot Power Limit Scale value, specifies the
upper limit on power supplied by slot.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00h”.
Reset to 00b.
Specifies the scale used for the Slot Power Limit Value.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00b”.
Reset to 00b.
Reset to 0h.
DESCRIPTION
PCI Express® Dual UART
PI7C9X7952
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