PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 37

• Manufacturer Part Number: PI7C9X7952AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7952AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.55. LINK STATUS REGISTER – OFFSET F0h
6.2.56. PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET
6.2.57. CAPABILITY VERSION – OFFSET 100h
6.2.58. NEXT ITEM POINTER REGISTER – OFFSET 100h
6.2.59. UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h
September 2009 – Revision 1.3
Pericom Semiconductor
100h
BIT
7
15:8
BIT
19:16
25:20
26
27
28
31:29
BIT
15:0
BIT
19:16
BIT
31:20
BIT
0
3:1
FUNCTION
Extended Synch
RsvdP
FUNCTION
Extended
Capabilities ID
FUNCTION
Capability Version
FUNCTION
Next Capability
Offset
FUNCTION
Training Error
Status
Reserved
FUNCTION
Link Speed
Negotiated Link
Width
Training Error
Link Training
Slot Clock
Configuration
Reserved
09-0087
RW1CS
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
When set, it transmits 4096 FTS ordered sets in the L0s state for
entering L0 state and transmits 1024 TS1 ordered sets in the L1 state
for entering L0 state
Reset to 0b.
Reset to 00h.
DESCRIPTION
Read as 0001h to indicate that these are PCI express extended
capability registers for advance error reporting.
DESCRIPTION
Indicates PCI-SIG defined PCI Express capability structure version
number.
Reset to 1h.
DESCRIPTION
Read as 00h. No other ECP registers.
Reset to 000h.
DESCRIPTION
Indicates the negotiated Link Speed of the given PCIe Link.
Defined encodings are: 0001b, which indicates 2.5 Gb/s Link
Reset to 1h.
Indicates the negotiated width of the given PCIe Link,
Reset to 000001b.
When set, indicates a Link training error occurred.
This bit is cleared by hardware upon successful training of the link to
the L0 link state.
Reset to 0b.
When set, indicates the link training is in progress. Hardware clears
this bit once link training is complete.
Reset to 0b.
It is not implemented. Hardwired to 0b.
Reset to 000b.
DESCRIPTION
When set, indicates that the Training Error event has occurred.
Reset to 0b.
Reset to 000b.
PCI Express® Dual UART
PI7C9X7952
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