Features
PCI Interfaces
• Industry-standard 32-bit, 66-MHz PCI
• Fully PCI Local Bus Specification,
• Supports up to nine PCI bus masters on
• Ten independent secondary clock
• Primary and secondary interfaces can be
• Secondary clock can either be derived
• Secondary clocks can be masked
T
system’s load capability limit beyond that of a
single PCI bus by allowing motherboard
designers to add more PCI devices or more PCI
option card slots than a single PCI bus can
support.
• Supports four independent delayed
• Supports up to nine secondary requests
• External arbiter support on the
• Supports CompactPCI Hot Swap
• CI Power management with D3Hot
• Supports Bus Locking mechanism
• VGA/Palette memory and I/O decoding
• Optional non-posted entry flush upon
• Compatible with existing solutions from
he Tsi350 makes it possible to extend a
bridge
Revision 2.3 compliant
the secondary interface
outputs to the secondary slots
operated using asynchronous clocks
from the input primary clock or supplied
by an external clock source
through the GPIO interface during
power up
transactions in each direction
and grants
secondary bus
functionality
support with option to disable clocks
during D3Hot state
options
posted writes traveling the same
direction
Intel, TI, PLX, and Pericom
Tsi350
PCI-to-PCI Bridge
The Tundra Semiconductor Tsi350 is a PCI-to-PCI bridge that is fully
compliant with PCI Local Bus Specification, Revision 2.3. The Tsi350 has
sufficient clock and arbitration pins to support nine PCI bus master devices
directly on its secondary interface.
The Tsi350 allows the two PCI buses to operate concurrently. This means that
a master and a target on the same PCI bus can communicate while the other
PCI bus is busy. This traffic isolation may increase system performance in
applications such as multimedia.
The Tsi350 makes it possible to extend a system’s load capability limit beyond
that of a single PCI bus by allowing motherboard designers to add more PCI
devices or more PCI option card slots than a single PCI bus can support.
The Tsi350 has two identical PCI Interfaces that each handle PCI transactions
for its respective bus, and, depending on the type of transaction, can act as
either a bus master or a bus slave. These interfaces transfer data and control
information flowing to and from the blocks shown below.
Block Diagram
66 MHz / 32-bit
PCI Bus
Boundary Scan
IEEE1149.1
JTAG
Posted
Posted
Queue
™
Buffer
Write
Logic
Mux
Clocking/
Decoder
Posted
Posted
Queue
Address
Buffer
Non-
Non-
Reset
Posted
Posted
Queue
Buffer
Non-
Non-
Logic
Posted
Posted
Queue
Mux
Buffer
Write
Bus Arbiter
Secondary
Swap
Hot
80D5000_BK001_02
66 MHz / 32-bit
PCI Bus