DS08MB200TSQX/NOPB National Semiconductor, DS08MB200TSQX/NOPB Datasheet - Page 5

• Manufacturer Part Number: DS08MB200TSQX/NOPB
• Description: IC MUX/BUFFER DUAL 800MBPS 48LLP
• Manufacturer: National Semiconductor
• Type: MUXr

Specifications of DS08MB200TSQX/NOPB

• Tx/rx Type: LVDS
• Delay Time: 1.0ns
• Capacitance - Input: 3.5pF
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 275mA
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Number Of Elements: 3
• Number Of Receivers: 3
• Number Of Drivers: 3
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Output Type: Repeater
• Differential Output Voltage: 500mV
• Transmission Data Rate: 800Mbps
• Propagation Delay Time: 2.5ns
• Power Dissipation: 5.2W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS08MB200TSQX/NOPB; DS08MB200TSQX

SUPPLY CURRENT (Static)
I
I
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
t
t
t
t
t
t
t
t
t
CC
CCZ
LHT
HLT
PLHD
PHLD
SKD1
SKCC
JIT
ON
ON2
OFF
Symbol
Note 8: Typical parameters are measured at V
Note 9: Differential output voltage V
Note 10: Output offset voltage V
Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V
400 MHz, t
Note 13: Deterministic Jitter, or D
voltage = V
Note 14: Total Jitter, or T
voltage = V
Note 15: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
Supply Current
Supply Current - Powerdown Mode ENA_0 = ENB_0 = ENL_0= ENA_1 =
Differential Low to High Transition
Time
Differential High to Low Transition
Time
Differential Low to High Propagation
Delay
Differential High to Low Propagation
Delay
Pulse Skew
Output Channel to Channel Skew
Jitter
(Note 11)
LVDS Output Enable Time
LVDS Output Enable time from
powerdown mode
LVDS Output Disable Time
r
ID
ID
= t
= 500mV, K28.5 pattern at 800 Mbps, t
= 500mV, 2
f
= 50ps (20% to 80%).
7-1
J
Parameter
, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input
PRBS pattern at 800 Mbps, t
OS
J
, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been subtracted. The input
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
OD
is defined as ABS(OUT+–OUT−). Differential input voltage V
DD
= 3.3V, T
r
= t
All inputs and outputs enabled and
active, terminated with differential load of
100Ω between OUT+ and OUT-.
ENB_1 = ENL_1 = L
Use an alternating 1 and 0 pattern at 200
Mb/s, measure between 20% and 80% of
V
Use an alternating 1 and 0 pattern at 200
Mb/s, measure at 50% V
input to output.
|t
Difference in propagation delay (t
t
15)
RJ - Alternating 1 and 0 at 400 MHz (Note
12)
DJ - K28.5 Pattern, 800 Mbps (Note 13)
TJ - PRBS 2
14)
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from TRI-STATE to active.
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from Powerdown to active
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to TRI-STATE
or powerdown.
f
PHLD
r
= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
PLHD
OD
= t
A
= 25°C. They are for reference purposes, and are not production-tested.
f
. (Note 15)
= 50ps (20% to 80%).
) among all output channels. (Note
–t
PHLD
| (Note 15)
7
-1 Pattern, 800 Mbps (Note
Conditions
5
OD
between
PLHD
ID
is defined as ABS(IN+–IN−).
or
Min
(Note 8)
Typ
225
170
170
0.6
1.0
1.0
1.3
0.5
25
50
15
16
10
ID
= 500mV, 50% duty cycle at
Max
275
250
250
115
4.0
2.5
2.5
1.5
1.5
75
34
34
20
12
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psrms
Units
psp-p
psp-p
mA
mA
ps
ps
ns
ns
ps
ps
µs
µs
ns