PCA9510AD,112 NXP Semiconductors, PCA9510AD,112 Datasheet
PCA9510AD,112
Specifications of PCA9510AD,112
935280025112
PCA9510AD
Related parts for PCA9510AD,112
PCA9510AD,112 Summary of contents
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PCA9510A Hot swappable I Rev. 04 — 18 August 2009 1. General description The PCA9510A is a hot swappable I insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected ...
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... NXP Semiconductors 3. Applications I cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system 4. Feature selection Table 1. Feature selection chart Feature Idle detect High-impedance SDA, SCL pins for V Rise time accelerator circuitry on SDAn and SCLn pins ...
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... NXP Semiconductors 6. Block diagram PCA9510A SDAIN CONNECT 100 k RCH1 100 k RCH2 SCLIN CONNECT 0.55V / CC 0.45V CC UVLO 100 s ENABLE DELAY Fig 1. Block diagram of PCA9510A PCA9510A_4 Product data sheet Hot swappable I BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT ENABLE 1 VOLT PRECHARGE BACKPLANE-TO-CARD CONNECTION CONNECT STOP BIT AND BUS IDLE 0 ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning ENABLE SCLOUT SCLIN Fig 2. 7.2 Pin description Table 3. Symbol ENABLE SCLOUT SCLIN GND READY SDAIN SDAOUT V CC PCA9510A_4 Product data sheet SDAOUT PCA9510AD 3 6 SDAIN GND 4 5 READY 002aab782 Pin configuration for SO8 Pin description ...
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... NXP Semiconductors 8. Functional description Refer to 8.1 Start-up An undervoltage and initialization circuit holds the parts in a disconnected state which presents high-impedance to all SDAn and SCLn pins during power-up. A LOW on the ENABLE pin also forces the parts into the low current disconnected state when the I essentially zero ...
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... NXP Semiconductors 8.3 Maximum number of devices in series Each buffer adds about 0.1 V dynamic level offset with the offset larger at higher temperatures. Maximum offset (V level at the signal origination end (master) is dependent upon the load and the only specification point is the I lightly loaded the V after four buffers would be 0 ...
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... NXP Semiconductors 8.4 Propagation delays The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides ...
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... NXP Semiconductors (1) Unshaded area indicates recommended pull-up. Fig (1) Unshaded area indicates recommended pull-up. Fig 6. 8.8 Hot swapping and capacitance buffering application Figure 7 advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements diffi ...
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... NXP Semiconductors See Application Note AN10160, ‘Hot Swap Bus Buffer’ for more information on applications and technical assistance. BACKPLANE CONNECTOR BACKPLANE BD_SEL SDA SCL Remark: The PCA9510A can be used in any combination depending on the number of rise time accelerators that are needed by the system. Normally only one PCA9510A would be required per bus. ...
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... NXP Semiconductors BACKPLANE CONNECTOR BACKPLANE SDA SCL Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9510A in a PCI system ENABLE SDA1 SDAIN SCLIN SCL1 to other System 1 devices Remark: See Application Note AN255, ‘I optimized for long distance transmission of the I Fig 9 ...
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... NXP Semiconductors Fig 10. System with disparate V 9. Application design-in information Fig 11. Typical application 10. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol oper T stg j(max) [1] Voltages with respect to pin GND. PCA9510A_4 Product data sheet R drop ...
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... NXP Semiconductors 11. Characteristics Table 5. Characteristics +85 C; unless otherwise specified. CC amb Symbol Parameter Power supply V supply voltage CC I supply current CC I Shut-down mode supply CC(sd) current Start-up circuitry V precharge voltage pch V HIGH-level input voltage IH(ENABLE) on pin ENABLE V LOW-level input voltage ...
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... NXP Semiconductors Table 5. Characteristics …continued +85 C; unless otherwise specified. CC amb Symbol Parameter Input-output connection V offset voltage offset t LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay C SCL and SDA input i(SCL/SDA) capacitance V LOW-level output voltage OL I input leakage current ...
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... NXP Semiconductors 11.1 Typical performance characteristics 3 (mA) 3.3 2.9 2.5 40 +25 Fig 12. I versus temperature CC Fig 14. Connection circuitry V PCA9510A_4 Product data sheet 002aab588 PHL (ns) 3.3 V 2 amb Fig 13. Input/output t 350 (mV) 250 150 3 Rev. 04 — 18 August 2009 PCA9510A 2 Hot swappable I C-bus and SMBus bus buffer ...
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... NXP Semiconductors 11.2 Timing diagrams SDAn/SCLn ENABLE READY Fig 15. Timing for idle(READY) SDAIN SCLIN SCLOUT SDAOUT ENABLE READY t is only applicable after the t stp(READY) Fig 16. t that can occur after t stp(READY) SCLIN, SDAIN, SCLOUT, SDAOUT ENABLE READY t is only applicable after the t stp(READY) Fig 17 ...
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... NXP Semiconductors 12. Test information R = load resistor load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 18. Test circuitry for switching times PCA9510A_4 Product data sheet Hot swappable PULSE DUT GENERATOR Rev. 04 — 18 August 2009 PCA9510A ...
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... NXP Semiconductors 13. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 8. Acronym AdvancedTCA CDM cPCI DUT ESD HBM 2 I C-bus MM PCI PICMG RC SMBus ...
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... NXP Semiconductors 16. Revision history Table 9. Revision history Document ID Release date PCA9510A_4 20090818 • Modifications: Section 8.7 “Resistor pull-up value “... always choose R maximum.” to “always choose 3.6 V maximum.” CC • Updated – changed from “rise time < 20 ns” to “rise time = 20 ns” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 5 8.1 Start-up 8.2 Connect circuitry 8.3 Maximum number of devices in series . . . . . . . 6 8.4 Propagation delays . . . . . . . . . . . . . . . . . . . . . . 7 8 ...