MAX3693ECJ Maxim Integrated Products, MAX3693ECJ Datasheet - Page 5
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MAX3693ECJ
Manufacturer Part Number
MAX3693ECJ
Description
IC SERIALIZR 622MBPS LVDS 32TQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX3693ECJ.pdf
(8 pages)
Specifications of MAX3693ECJ
Function
Serializer
Data Rate
622Mbps
Input Type
LVDS
Output Type
PECL
Number Of Inputs
4
Number Of Outputs
1
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX3693ECJ
Manufacturer:
MAXIM/美信
Quantity:
20 000
Company:
Part Number:
MAX3693ECJ+
Manufacturer:
AKM
Quantity:
137
Company:
Part Number:
MAX3693ECJ+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Company:
Part Number:
MAX3693ECJ+T
Manufacturer:
Maxim Integrated
Quantity:
10 000
The MAX3693 serializer comprises a 4-bit parallel input
register, a 4-bit shift register, control and timing logic, a
PECL output buffer, LVDS input/output buffers, and a
frequency-synthesizing PLL (consisting of a phase/
frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and prescaler). This device con-
verts 4-bit-wide, 155Mbps data to 622Mbps serial data
(Figure 1).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
Figure 1. Functional Diagram
_______________Detailed Description
PCLKI+
PCLKI-
RCLK+
RCLK-
PD3+
PD2+
PD1+
PD0+
PD3-
PD2-
PD1-
PD0-
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
_______________________________________________________________________________________
with Clock Synthesis and LVDS Inputs
PHASE/FREQ
DETECT
PARALLEL
REGISTER
INPUT
4-BIT
PRESCALER
FIL+ FIL- CKSET
VCO
The incoming parallel data is clocked into the
MAX3693 on the rising transition of the parallel-clock-
input signal (PCLKI). The control and timing logic
ensure proper operation if the parallel-input register is
latched within a window of time that is defined with
respect to the parallel-clock-output signal (PCLKO).
PCLKO is the synthesized 622Mbps internal serial-
clock signal divided by four. The allowable PCLKO-to-
PCLKI skew is 0 to +4ns. This defines a timing window
at about the PCLKO rising edge, during which
a PCLKI rising edge may occur (Figure 2).
PCLKO+ PCLKO-
CONTROL
LVDS
SHIFT
LATCH
REGISTER
SHIFT
4-BIT
MAX3693
PECL
SD+
SD-
5