SCAN12100TYA/NOPB National Semiconductor, SCAN12100TYA/NOPB Datasheet - Page 27

• Manufacturer Part Number: SCAN12100TYA/NOPB
• Description: IC SERIAL/DESERIAL CPRI 100-TQFP
• Manufacturer: National Semiconductor
• Series: SCANr

Specifications of SCAN12100TYA/NOPB

• Function: Serializer/Deserializer
• Data Rate: 614.4Mbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 10
• Number Of Outputs: 10
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SCAN12100TYA

Bit
D15–D2
D1-D0
Bit
D15-D13
D12
D11
D10
D9-D0
Bit
D15–D0
Bit
D15–D2
D1
D0
Bit
D15–D9
D8
D7-D0
4.1.10 Speed Mode
4.1.11 BIST Status
4.1.12 Reserved
4.1.13 Run DCM
4.1.14 Loss of Frame (LOF)
Address: 0Ah Value: 0000h
Address: 0Bh Value: 0100h
Address: 0Ch Value: 0249h
Address: 0Dh Value: 0000h
Address: 10h Value: 0000h
Default
14'd0
2'd0
Default
3'd0
1'b1
1'b0
1'b0
10'd0
Default
16'h0249
Default
14'd0
1'b0
1'b0
Default
7'd0
1'd0
8'h00
Bit Name
Reserved
SPMODE
Bit Name
Reserved
BIST Stopped
BIST Error
BIST Detect
Error Count
Bit Name
Reserved
Bit Name
Reserved
Reserved
Run DCM
Bit Name
Reserved
LOF Status
LOF Count
Access
Access
Access
Access
Access
RW
WC
WC
WC
RC
RC
RC
RC
RO
RC
RC
—
—
—
Bit Description
Reserved for future use. Returns undefined value when read.
Sets CPRI speed mode when SPMODE[1:0] pins are low or floating.
Bit Description
Reserved for future use. Returns undefined value when read.
BIST Stopped: A value [1] will occur when Rx BIST verifier has been
stopped.
BIST Error: Returns a [1] value when the receive BIST verifier has been
stopped or the BIST error count is greater than 10d'0. Returns a [0] value
if no BIST errors.
Rx BIST verifier starts comparing the input data sequence after 3 cycles
of properly aligned header sequences have been detected. A value of
[1] implies that BIST verifier is checking the pattern. A read operation will
NOT clear this bit nor will it reset the alignment of the pattern.
This register displays the cumulative number of receive bit errors. The
error count starts once a BIST pattern has been detected and the receive
BIST verifier is enabled. This register counts a maximum of 10'h3FF
errors and remains static as soon as BIST is stopped on the Rx verifier
side. A read operation during the BIST enabled mode will clear the error
count.
Bit Description
Reserved for future use. Returns undefined value when read.
Bit Description
Reserved for future use. Returns undefined value when read.
Reserved for future use. Returns undefined value when read.
Writing a [1] runs DCM.
Bit Description
Reserved for future use. Returns undefined value when read.
CPRI loss of Frame (LOF) status. A [1] value indicates loss of CPRI
frame. A [0] value indicates frame acquired.
Loss of frame count. The maximum count which can be accumulated in
this register is 8'hFF.
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