SCAN12100TYA/NOPB National Semiconductor, SCAN12100TYA/NOPB Datasheet - Page 14

• Manufacturer Part Number: SCAN12100TYA/NOPB
• Description: IC SERIAL/DESERIAL CPRI 100-TQFP
• Manufacturer: National Semiconductor
• Series: SCANr

Specifications of SCAN12100TYA/NOPB

• Function: Serializer/Deserializer
• Data Rate: 614.4Mbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 10
• Number Of Outputs: 10
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SCAN12100TYA

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Initial power up
TXPWDNB and RXPWDNB low for
RESETB low for
Write “0” to MDIO RESETB register
SPMODE change
TXCLK missing for
RXCLK missing for
TRSTB (IEEE 1149.1 interface)
Deterministic FIFO Delay at Start Up
To ensure synchronous operation, REFCLK, TXCLK, and
RXCLK should be stable and the receiver synchronized be-
fore data is sent into or out of the parallel buses.
SCAN12100 CLOCK DOMAINS
Most SerDes have only two clocks: a reference clock (that
also acts as a transmit clock) and a receive recovered clock.
The SCAN12100 has additional clocking features beneficial
for RE applications. The chip’s receiver PLL circuitry is inde-
pendent of REFCLK and has an integrated oscillator, allowing
the receiver to lock to the incoming REC stream and syn-
chronize the RE without losing lock when REFCLK switches
from local to recovered clock.
≥
1 us
≥
≥
Reset Type
7 cycles
7 cycles (Read Mode)
≥
1 us
FIGURE 2. SCAN12100 Clock Domains
TABLE 1. Reset Conditions
All internal states and registers held at reset for 150 ms after power on. This
reset period is based on an internal counter monitoring the 30.72 MHz
REFCLK input signal.
All internal states and registers are reset
Logic reset (including MDIO)
Logic reset (excluding MDIO)
Logic reset (excluding MDIO)
Transmit FIFO flushed, transmit read/write pointers reset
Receive FIFO flushed, receive read/write pointers reset
Only IEEE 1149.1 state machine is reset
14
The sharing of clocks in these architectures, however, can
cause loss of lock issues during RE synchronization. To pro-
vide seamless base station synchronization, the SCAN12100
features independent transmit and receive PLLs and four
clock signals.
Once the RE is synchronized to the REC, all clocks are syn-
chronous and the four clock domains become one clock
domain. Holding TXCLK (and RXCLK if in read mode) static
high or static low until the RE is synchronized to the REC en-
sures the on-chip FIFOs are flushed and reset. Once the
system is synchronous, the SCAN12100 chip delays are con-
What is Reset
20209501