SCAN12100TYA/NOPB National Semiconductor, SCAN12100TYA/NOPB Datasheet - Page 10

• Manufacturer Part Number: SCAN12100TYA/NOPB
• Description: IC SERIAL/DESERIAL CPRI 100-TQFP
• Manufacturer: National Semiconductor
• Series: SCANr

Specifications of SCAN12100TYA/NOPB

• Function: Serializer/Deserializer
• Data Rate: 614.4Mbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 10
• Number Of Outputs: 10
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SCAN12100TYA

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t
CDET OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1)
t
CDET OUTPUT TIMING SPECIFICATIONS (Write Mode RXCLKMODE=0) (Note 5)
t
t
SYSCLK LVDS OUTPUT TIMING SPECIFICATIONS
t
JIT
t
MDC/MDIO TIMING SPECIFICATIONS (Clause 45)
f
t
t
t
t
MINIMUM PULSE WIDTH, Hardware Reset (Note 12)
t
t
t
JTAG TIMING SPECIFICATIONS
f
t
t
t
t
t
t
t
t
t
DELAY CALIBRATION MEASUREMENT (DCM) (Notes 11, 13, 14)
T
T
T
T
T
T
R
PDCD
S-C
H-C
SYSCLKNDC
R
MDC
S-MDIO
H-MDIO
D-MDIO
X-MDIO
TX-RST
RX-RST
RST
JTAG
R-J
F-J
S-TDI
H-TDI
S-TMS
H-TMS
W-TCK
W-TRST
REC
14
offset
ser
des
in-out
out-in
, t
, t
Symbol
SYSCLK
F
F
Output data transition time
CDET Propagation Delay
Setup Time
Hold Time
Duty cycle
Cycle to cycle jitter
Output transition time
MDC Frequency
Setup Time
Hold Time
Delay Time
Transition Time
Transmiter Reset
Receiver Reset
SerDes Reset
JTAG TCK Frequency
TDO data transition time (20% to
80%)
Setup Time TDI to TCK High or Low
Hold Time TDI to TCK High or Low
Setup Time TMS to TCK High or
Low
Hold Time TMS to TCK High or Low
TCK Pulse Width
TRSTB Pulse Width
Recovery Time TRSTB to TCK
T
T
Serializer Delay Accuracy
Deserializer Delay Accuracy
T
T
14
offset
in-out
out-in
Delay Accuracy
Delay Accuracy
Delay Accuracy
Delay Accuracy
Parameter
For ROUT [0-9], LOCK, etc. pins.
Measured between 20% and 80%
levels
RXCLK rising or falling edge to
CDET
CDET valid to RXCLK rising or
falling edge
RXCLK rising or falling edge to
CDET valid
(Note 11)
Between 20% and 80% levels (Note
11)
MDIO (input) valid to MDC rising
clock
MDC rising edge to MDIO (input)
invalid
MDIO (output) delay from MDC
rising edge
Measured at MDIO when used as
output, CL = 470 pF
TXPWDNB = 0
RXPWDNB = 0
RESETB = 0
R
Receive and Transmit PLLs locked
to valid hyperframe data.
L
= 1000Ω, C
Condition
L
10
= 15 pF
Min
2.6
2.6
0.1
2.5
40
10
10
25
10
14
2
0
0
2
2
2
2
(Note 2)
0.35
Typ
40
4
1
1
1
1
2
± 1200
± 1200
± 1200
± 1200
± 800
± 800
Max
300
0.3
2.5
60
65
6
ps p-p
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
%