AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 30

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
VERTICAL TIMING GENERATION
The AD9898 provides a very flexible solution for generating
vertical CCD timing and can support multiple CCDs and dif-
ferent system architectures. The 4-phase vertical transfer clocks
V1–V4 are used to shift each line of pixels into the horizontal
output register of the CCD. The AD9898 vertical outputs can
be individually programmed into four different vertical pulse
patterns identified as VTP0, VTP1, VTP2, and VTP3. Each
vertical pulse pattern is a unique set of preconfigured V1–V4
sequences. Once the vertical patterns have been configured
using the registers in Table XVII, pointer registers are used to
select which region of the CCD a particular vertical pattern is
output in. The pointer registers are described in Table XV.
Up to five unique CCD regions may be specified. The readout
of the entire field is constructed by combining one or more of
the individual regions sequentially. With up to five region areas
available, different steps of the readout, such as high speed line
shifts and vertical image transfer, can be supported.
Creating Vertical Sequences
Figures 28, 29, and 30 provide an overview of how the vertical
timing is generated in four basic steps.
Step 1
Create the Individual Pulses for Patterns VTP0, VTP1, VTP2,
and VTP3 (See Figure 28)
The registers shown in Table XV are used to generate the
individual vertical timing pulses, as shown in Figure 28. The
VTPLENx determines the number of pixels between pulse
repetitions. The start polarity (VxSTARTPOLx) sets the start-
ing polarity of the vertical sequence and can be programmed
high or low. The first toggle position (VxTOG1POSx) and
second toggle position (VxTOG2POSx) are the pixel locations
within the line where the pulse transitions.
HD
V1
V2
V3
V4
Figure 28. Step 1: Create Individual Vertical Pulses for VTP0, VTP1, VTP2, and VTP3 Patterns
0
PROGRAMMABLE CLOCK POSITIONS
10. V4STARTPOLx = 0
11. V4TOG1x[8:0] = 20
12. V4TOG2x[8:0] = 160
10
1
4
7
1. V1STARTPOLx = 0
2. V1TOG1x[8:0] = 50
3. V1TOG2x[8:0] = 130
4. V2STARTPOLx = 1
5. V2TOG1x[8:0] = 30
6. V2TOG2x[8:0] = 150
7. V3STARTPOLx = 1
8. V3TOG1x[8:0] = 110
9. V3TOG2x[8:0] = 180
11
5
2
50
VTPLENx [8:0] = 210
100
8
3
150
6
12
9
200
–30–
Step 2
Create the Individual Vertical Sequences (See Figure 29)
The individual vertical sequences are created by assigning pulse
repetitions to patterns VTP0, VTP1, VTP2, and VTP3, using
VTPREPx registers in Table XVI. The number of repetitions
(VTPREPx) determines the number of pulse repetitions desired
within a single line. Programming 1 for VTPREPx gives a single
pulse, while setting it to 0 will provide a fixed dc output based
on the start polarity value. Figure 29 shows an example of a VTPx
sequence of two VTPx patterns made by setting VTPREPx = 2.
Step 3
Output Vertical Sequences into CCD Regions (See Figure 30)
The AD9898 arranges individual sequences into CCD regions
through the use of sequence pointers (VTPSEQPTRx) and
vertical transfer pattern select (VTPSELx) registers, as described
in Table XVI. The VTPSEQPTRx registers are used to point to
a desired VTPSELx register whose value determines what VTPx
pattern will be output on the V1–V4 pins. For example, if
VTPSEQPTR0 = 1 and VTPSEL1 = 2, the VTP2 pulse pattern
would output while operating in Region 0 of the CCD.
Step 4
Combining CCD Regions (See Figure 30)
The entire field readout can be built by combining multiple regions
by using mode registers SCP0, SCP1, SCP2, SCP3, and SCP4.
The individual CCD regions are combined into a complete field
readout using the sequence change position (SCPx) pointers as
described in Table XVII. Figure 30 shows how each field is
divided into multiple regions which allows the user to change
vertical timing during various stages of the image readout. The
boundaries of each region are defined by the sequence change
position (SCP). Each SCP is an 8-bit value representing the line
number boundary region. A total of four SCPs allow up to five
different regions in the field to be defined. The first SCP0 is
always hard coded to line zero, and the remaining four SCPs are
register programmable.
250
300
350
400
REV. 0