AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 18

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
VD SYNCHRONOUS AND ASYNCHRONOUS REGISTER
OPERATION
There are two types of control registers, VD synchronous and
VD asynchronous, as indicated in the address column of Table I.
Register writes to synchronous and asynchronous type registers
operate differently, as described below. Writes to system, Mode_A,
and Mode_B registers occur asynchronously.
Asynchronous Register Operation
For VD asynchronous register writes, SDATA data is stored
directly into the serial register at the rising edge of SL. As a
result, register operation begins immediately after the rising
edge of SL.
SDATA
CLI
SCK
HD
VD
SL
1. ALL SL PULSES ARE IGNORED UNTIL THE LSB OF THE LAST DATA N WORD IS CLOCKED IN.
2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.
ADDRESS [7:0]
ADDRESS
8-BIT
PROGRAMMING OF VD SYNCHRONOUS
TYPE REGISTERS MUST BE COMPLETED
AT LEAST 4 CLI CYCLES BEFORE THE
FALLING EDGE OF VD.
NUMBER WRITES N [23:0]
NUMBER OF 32-BIT
Figure 9. VD Synchronous Type Register Writes
DATA WRITES (N)
Figure 8. System and Mode Register Writes
REGISTER WRITES BEGIN AT THE NEXT VD
FALLING EDGE.
OPERATION OF VD SYNCHRONOUS TYPE
DATA 1 [31:0]
1
DATA 1 [31:0]
–18–
VD Synchronous Register Operation
For VD synchronous type registers, SDATA data is temporarily
stored in a buffer register at the rising edge of SL. This data is
held in the buffer register until the next falling edge of VD is
applied. Once the next falling edge of VD occurs, the buffered
SDATA data is loaded into the serial register and the register
operation begins (see Figure 9).
All control registers at the following addresses are VD Synchro-
nous type registers—Addr: 0x0A, 0x0B, 0x0C, 0x0D, and 0x0E
(see Table I).
DATA 2 [31:0]
DATA 2 [31:0]
1
1
DATA N [31:0]
DATA N [31:0]
2
REV. 0