AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 4

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
TIMING SPECIFICATIONS
C
Table 2.
Parameter
MASTER CLOCK (CLI)
AFE
SERIAL INTERFACE
H-COUNTER RESET SPECIFICATIONS
TIMING CORE SETTING RESTRICTIONS
1
2
3
4
5
6
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Only applies to slave mode operation. The inhibited area for SHP is needed to meet the timing requirements for t
When 0x34[2:0] HxBLKRETIME bits are enabled, the inhibit region for SHD location changes to inhibit region for SHP location.
When sequence register 0x09[23:21] HBLK masking registers are set to 0, the H-edge reference becomes H × NEGLOC.
The H-clock signals that have SHP/SHD inhibit regions depends on the HCLK mode: Mode 1 = H1, Mode 2 = H1, H2, and Mode 3 = H1, H3.
These specifications apply when H1POL, H2POL, RGPOL, and HLPOL are all set to 1 (default setting).
L
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal
CLPOB Pulse Width (Programmable)
HD Pulse Width
VD Pulse Width
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Rising Edge to SDATA Hold
HD Pulse Width
VD Pulse Width
SHP Rising Edge to SHD Rising Edge
AFE Pipeline Delay
VD Falling Edge to HD Falling Edge
HD Falling Edge to CLI Rising Edge
CLI Rising Edge to SHPLOC (Internal
Inhibited Region for SHP Edge Location
Inhibited Region for SHP or SHD with
Inhibited Region for DOUTPHASE Edge
= 20 pF, AVDD = DVDD = 1.8 V, f
(See Figure 19)
Respect to H-Clocks(See Figure 19)
Location (See Figure 19)
Pixel Position 0
Sample Edge)
RETIME = 0, MASK = 0
RETIME = 0, MASK = 1
RETIME = 1, MASK = 0
RETIME = 1, MASK = 1
CLI
1
3, 4, 5, 6
= 65 MHz, unless otherwise noted.
2
Symbol
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
CONV
ADC
CLIDLY
S1
COB
SCLK
LS
LH
DS
DH
VDHD
HDCLI
CLISHP
SHPINH
SHDINH
SHDINH
SHPINH
SHPINH
DOUTINH
Rev. C | Page 4 of 56
Min
15.38
6.9
6.9
2
t
1 HD period
40
10
10
10
10
t
1 HD period
0
3
3
50
H × NEGLOC − 15
H × POSLOC − 15
H × NEGLOC − 15
H × POSLOC − 15
SHDLOC + 0
CONV
CONV
Typ
7.7
5
7.7
16
20
Max
8.9
8.5
VD period − t
t
t
64/0
H × NEGLOC − 0
H × POSLOC − 0
H × NEGLOC − 0
H × POSLOC − 0
SHDLOC + 15
CONV
CONV
CLISHP
− 2
− 2
for proper H-counter reset operation.
CONV
Unit
Pixels
ns
ns
ns
ns
Cycles
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
See Figure 15
See Figure 19
See Figure 20
See Figure 56
See Figure 53
Edge location
Edge location
Edge location
Edge location
Edge location
Edge location