AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 46

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
Table 29. Timing Core Registers
Address
30
31
32
33
34
Data Bit
Content
[5:0]
[7:6]
[13:8]
[15:14]
[16]
[27:17]
[5:0]
[7:6]
[13:8]
[15:14]
[16]
[27:17]
[5:0]
[7:6]
[13:8]
[15:14]
[16]
[27:17]
[5:0]
[7:6]
[13:8]
[15:14]
[16]
[27:17]
[0]
[1]
[2]
[3]
[7:4]
[27:8]
Default
Value
0
20
0
1
0
20
0
1
0
20
0
1
0
10
0
1
0
0
0
0
0
Update
Type
SCK
SCK
SCK
SCK
SCK
Name
H1POSLOC
Unused
H1NEGLOC
TESTMODE
H1POL
Unused
H2POSLOC
Unused
H2NEGLOC
TESTMODE
H2POL
Unused
Unused
HLNEGLOC
TESTMODE
HLPOL
Unused
Unused
RGNEGLOC
TESTMODE
RGPOL
Unused
H2BLKRETIME
HLBLKRETIME
HL_HBLK_EN
Unused
HLPOSLOC
RGPOSLOC
H1BLKRETIME
HCLK_WIDTH
Rev. C | Page 46 of 56
Description
H1 rising edge location.
Set unused bits to 0.
H1 falling edge location.
Test operation only. Set to 0.
H1 polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
H2 rising edge location.
Set unused bits to 0.
H2 falling edge location.
Test operation only. Set to 0.
H2 polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
HL rising edge location.
Set unused bits to 0.
HL falling edge location.
Test operation only. Set to 0.
HL polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
RG rising edge location.
Set unused bits to 0.
RG falling edge location.
Test operation only. Set to 0.
RG polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
Retime H1 HBLK to internal clock.
0 = no retime.
1 = enable retime.
Retime H2 HBLK to internal clock.
Retime HL HBLK to internal clock.
Enables HBLK for HL output.
0 = disable.
1 = enable.
Enables wide horizontal clocks during HBLK interval.
0 = disable (see Table 12).
Set unused bits to 0.
1, 2
1
1, 2