AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 50

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
Table 32. Update Control Registers
Address
60
61
62
63
64
65
66
Data Bit
Content
[15:0]
[27:16]
[15:0]
[27:16]
[15:0]
[27:16]
[15:0]
[27:16]
[15:0]
[27:16]
[15:0]
[27:16]
[15:0]
[27:16]
Default
Value
1803
E7FC
F8FD
0702
FFF9
0006
FFFF
Update
Type
SCK
SCK
SCK
SCK
SCK
SCK
SCK
Name
Unused
Unused
Unused
MISC_UPDT_VD
Unused
Unused
Unused
Unused
AFE_UPDT_SCK
AFE_UPDT_VD
MISC_UPDT_SCK
VDHD_UPDT_SCK
VDHD_UPDT_VD
TGCORE_UPDT_SCK
Rev. C | Page 50 of 56
Description
Enable SCK update of AFE registers. Each bit corresponds to
one address location.
AFE_UPDT_SCK[0] = 1; update Address 0x00 on SCK rising edge.
AFE_UPDT_SCK[1] = 1; update Address 0x01 on SCK rising edge.
…
AFE_UPDT_SCK[15] = 1; update Address 0x0F on SCK rising edge.
Set unused bits to 0, if accessed.
Enable VD update of AFE registers. Each bit corresponds to
one address location.
AFE_UPDT_VD[0] = 1; update Address 0x00 on VD rising edge.
AFE_UPDT_VD[1] = 1; update Address 0x01 on VD rising edge.
…
AFE_UPDT_VD[15] = 1; update Address 0x0F on VD rising edge.
Set unused bits to 0, if accessed.
Enable SCK update of miscellaneous registers. Each bit corresponds to
one address location.
MISC_UPDT_SCK[0] = 1; update Address 0x10 on SCK rising edge.
MISC_UPDT_SCK[1] = 1; update Address 0x11 on SCK rising edge.
…
MISC_UPDT_SCK[15] = 1; update Address 0x1F on SCK rising edge.
Set unused bits to 0, if accessed.
Enable VD update of miscellaneous registers. Each bit corresponds to
one address location.
MISC_UPDT_VD[0] = 1; update Address 0x10 on VD rising edge.
MISC_UPDT_VD[1] = 1; update Address 0x11 on VD rising edge.
…
MISC_UPDT_VD[15] = 1; update Address 0x1F on VD rising edge.
Set unused bits to 0, if accessed.
Enable SCK update of VDHD registers. Each bit corresponds to
one address location.
VDHD_UPDT_SCK[0] = 1; update Address 0x20 on SCK rising edge.
VDHD_UPDT_SCK[1] = 1; update Address 0x21 on SCK rising edge.
…
VDHD_UPDT_SCK[15] = 1; update Address 0x22 on SCK rising edge.
Set unused bits to 0, if accessed.
Enable VD update of VDHD registers. Each bit corresponds to
one address location.
VDHD_UPDT_SCK[0] = 1; update Address 0x20 on VD rising edge.
VDHD_UPDT_SCK[1] = 1; update Address 0x21 on VD rising edge.
…
VDHD_UPDT_SCK[15] = 1; update Address 0x22 on VD rising edge.
Set unused bits to 0, if accessed.
Enable SCK update of timing core registers. Each bit corresponds to
one address location.
TGCORE_UPDT_SCK[0] = 1; update Address 0x30 on SCK rising edge.
TGCORE_UPDT_SCK[1] = 1; update Address 0x31 on SCK rising edge.
…
TGCORE_UPDT_SCK[15] = 1; update Address 0x37 on SCK rising edge.
Set unused bits to 0, if accessed.