X96010V14IZ Intersil, X96010V14IZ Datasheet - Page 21

• Manufacturer Part Number: X96010V14IZ
• Description: IC SENSOR CONDITIONER 14-TSSOP
• Manufacturer: Intersil
• Type: Sensor Conditionerr

Specifications of X96010V14IZ

• Input Type: Voltage
• Output Type: Voltage
• Interface: 2-Wire
• Current - Supply: 15mA
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

X96010 Memory Map
The X96010 contains a 144 byte array of mixed vola-
tile and nonvolatile memory. This array is split up into
three distinct parts, namely: (Refer to figure 14.)
– Look-up Table 1 (LUT1)
– Look-up Table 2 (LUT2)
– Control and Status Registers
Figure 14. X96010 Memory Map
The Control and Status registers of the X96010 are
used in the test and setup of the device in a system.
These registers are realized as a combination of both
volatile and nonvolatile memory. These registers
reside in the memory locations 80h through 8Fh. The
reserved bits within registers 80h through 86h, must
be written as “0” if writing to them, and should be
ignored when reading. Register bits shown as 0 or 1,
in Figure 4, must be written with the indicated value if
writing to them. The reserved registers, from 88h
through 8Fh, must not be written, and their content
should be ignored.
Both look-up tables LUT1 and LUT2 are realized as
nonvolatile EEPROM, and extend from memory loca-
tions 90h - CFh and D0h - 10Fh respectively. These
look-up tables are dedicated to storing data solely for
the purpose of setting the outputs of Current Genera-
tors I1 and I2 respectively.
All bits in both look-up tables are preprogrammed to
“0” at the factory.
Address
10Fh
D0h
CFh
FFh
8Fh
90h
80h
Control & Status
Look-up Table 2
Look-up Table 1
Registers
(LUT2)
(LUT1)
21
64 Bytes
64 Bytes
16 Bytes
Size
X96010
Addressing Protocol Overview
All Serial Interface operations must begin with a
START, followed by a Slave Address Byte. The Slave
address selects the X96010, and specifies if a Read or
Write operation is to be performed.
It should be noted that the Write Enable Latch (WEL)
bit must first be set in order to perform a Write opera-
tion to any other bit. (See “WEL: Write Enable Latch
(Volatile)” on page 13.) Also, all communication to the
X96010 over the 2-wire serial bus is conducted by
sending the MSB of each byte of data first.
The memory is physically realized as one contiguous
array, organized as 9 pages of 16 bytes each.
The X96010 2-wire protocol provides one address
byte, therefore the next few sections explain how to
access the different areas for reading and writing.
Figure 15. Slave Address (SA) Format
Slave Address
SA7
1
SA7 - SA4
SA3 - SA1
Bit(s)
Device Type
SA0
SA6
Identifier
0
SA5
1
SA4
Device Type Identifier
Device Address
Read or Write Operation Select
0
SA3
AS2
Description
Address
Device
SA2
AS1
AS0
SA1
Read or
Write
R/W
SA0
October 25, 2005
FN8214.1