PCA9698DGG,518 NXP Semiconductors, PCA9698DGG,518 Datasheet - Page 13

• Manufacturer Part Number: PCA9698DGG,518
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9698DGG,518

• Package / Case: 56-TSSOP
• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9698
• Number Of Lines (input / Output): 40.0 / 40.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I2C Bus
• Maximum Clock Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 40.0
• Number Of Output Lines: 40.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6281 - DAUGHTER CARD PCA9698 FOR OM6275
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935278614518; PCA9698DGG-T; PCA9698DGG-T

NXP Semiconductors
Table 8.
Legend: * default value.
PCA9698
Product data sheet
Address
20h
21h
22h
23h
24h
MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description
Register
MSK0
MSK1
MSK2
MSK3
MSK4
7.4.5 MSK0 to MSK4 - Mask interrupt registers
7.4.6 OUTCONF - output structure configuration register
These registers mask the interrupt due to a change in the I/O pins configured as inputs.
‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 9.
This register controls the configuration of the output ports as open-drain or totem-pole.
The 4 least significant bits control the output architecture for bank 0, 2 bits at a time.
The 4 most significant bits control the output architectures for bank 1 to bank 4, each bit
controlling one bank.
OUTx = 0: The I/Os are configured with an open-drain structure.
OUTx = 1: The I/Os are configured with a totem-pole structure.
Bit
Symbol
Default
Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).
OUT001 controls the output structure for IO0_0 and IO0_1
OUT023 controls the output structure for IO0_2 and IO0_3
OUT045 controls the output structure for IO0_4 and IO0_5
OUT067 controls the output structure for IO0_6 and IO0_7
OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7)
OUT2 controls the output structure for bank 2 (IO2_0 to IO2_7)
OUT3 controls the output structure for bank 3 (IO3_0 to IO3_7)
OUT4 controls the output structure for bank 4 (IO4_0 to IO4_7)
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
OUTCONF - output structure configuration register (address 28h) description
OUT4
7
1
All information provided in this document is subject to legal disclaimers.
Symbol
M0[7:0]
M1[7:0]
M2[7:0]
M3[7:0]
M4[7:0]
OUT3
40-bit Fm+ I
Rev. 3 — 3 August 2010
6
1
Access
R/W
R/W
R/W
R/W
R/W
OUT2
5
1
2
C-bus advanced I/O port with RESET, OE and INT
Value
1111 1111*
1111 1111*
1111 1111*
1111 1111*
1111 1111*
OUT1
4
1
OUT067
3
1
Mask Interrupt register bank 0
Mask Interrupt register bank 1
Mask Interrupt register bank 2
Mask Interrupt register bank 3
Mask Interrupt register bank 4
Description
OUT045
2
1
PCA9698
OUT023
© NXP B.V. 2010. All rights reserved.
1
1
OUT001
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0
1