ADV7194KST Analog Devices Inc, ADV7194KST Datasheet - Page 50

• Manufacturer Part Number: ADV7194KST
• Description: IC ENCODER VIDEO EXT-10 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7194KST

• Rohs Status: RoHS non-compliant
• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• For Use With: EVAL-ADV7194EB - BOARD EVAL FOR ADV7194
• Lead Free Status / RoHS Status: Not Compliant

ADV7194
Time, t
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears T
the horizontal signal. Time TTX
the source that is gated by the TTXREQ signal in order to deliver
TTX data.
With the programmability that is offered with TTXREQ signal
on the Rising/Falling edges, the TTX data is always inserted at
the correct position of 10.2 µs after the leading edge of Horizontal
Sync pulse, thus this enables a source interface with variable
pipeline delays.
The width of the TTXREQ signal must always be maintained
such that it allows the insertion of 360 (in order to comply with
the Teletext Standard PAL-WST) teletext bits at a text data rate
of 6.9375 Mbits/s, this is achieved by setting TC03–TC00 to 0.
The insertion window is not open if the Teletext Enable bit
(MR33) is set to 0.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is given as follows:
PD
, is the time needed by the ADV7194 to interpolate
TTX
TTXREQ
CVBS/Y
HSYNC
(6.9375 × 10
DATA
(27 MHz/4) = 6.75 MHz
t
t
TTX
SYNTTXOUT
SYNTTXOUT
PD
TELETEXT VBI LINE
= PIPELINE DELAY THROUGH ADV7194
DEL
t
PD
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
6
/6.75 × 10
= 10.2 s
= 10.2 µs after the leading edge of
TTX
DEL
ST
is the pipeline delay time by
10.2 s
6
t
) = 1.027777
SYNTTXOUT
TTX
DEL
TELETEXT INSERTION
t
PD
APPENDIX 5
RUN-IN CLOCK
45 BYTES (360 BITS) – PAL
PROGRAMMABLE PULSE EDGES
Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit
has a width of almost four clock cycles. The ADV7194 uses
an internal sequencer and variable phase interpolation filter
to minimize the phase jitter and thus generate a bandlimited
signal which can be output on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that
TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are Bits 47, 56, 65, and 74. This scheme
holds for all following cycles of 37 TTX bits, until all 360 TTX
bits are completed. All teletext lines are implemented in the
same way. Individual control of teletext lines are controlled
by Teletext Setup Registers.
ADDRESS & DATA