ADV7194KST Analog Devices Inc, ADV7194KST Datasheet - Page 18

• Manufacturer Part Number: ADV7194KST
• Description: IC ENCODER VIDEO EXT-10 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7194KST

• Rohs Status: RoHS non-compliant
• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• For Use With: EVAL-ADV7194EB - BOARD EVAL FOR ADV7194
• Lead Free Status / RoHS Status: Not Compliant

ADV7194
UNDERSHOOT LIMITER
A limiter is placed after the digital filters. This prevents any
synchronization problems for TVs. The level of undershoot is
programmable between –1.5 IRE, –6 IRE, –11 IRE when oper-
ating in 4× Oversampling Mode. In 2× Oversampling Mode the
limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing
Register 0.)
DIGITAL NOISE REDUCTION
DNR is applied to the Y data only. A filter block selects the
high frequency, low-amplitude components of the incoming
signal (DNR Input Select). The absolute value of the filter output
is compared to a programmable threshold value (DNR Thresh-
old Control). There are two DNR modes available: DNR Mode
and DNR Sharpness Mode.
In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub-
tracted from the original signal.
In DNR Sharpness Mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.
In MPEG systems it is common to process the video informa-
tion in blocks of 8 × 8 pixels for MPEG2 systems, or 16 × 16
pixels for MPEG1 systems (Block Size Control). DNR can be
applied to the resulting block transition areas that are known to
contain noise. Generally the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(Border Area Control).
It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the Block Offset
Control. (Mode Register 8, DNR Registers 0–2.)
DOUBLE BUFFERING
Double buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control
Register, V-Scale Register, U-Scale Register, Contrast Control
Register, Hue Adjust Register, and the Gamma Curve Select
bit. These registers are updated once per field on the falling
edge of the VSYNC signal. Double Buffering improves the over-
all performance of the ADV7194, since modifications to register
settings will not be made during active video, but take effect on
the start of the active video. (Mode Register 8.)
GAMMA CORRECTION CONTROL
Gamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-defined function. (Mode
Register 8, Gamma Correction Registers 0–13.)
NTSC PEDESTAL CONTROL
In NTSC mode it is possible to have the pedestal signal gener-
ated on the output video signal. (Mode Register 2.)
POWER-ON RESET
After power-up, it is necessary to execute a RESET operation.
A reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port such that the data
on the pixel inputs pins is ignored. See Appendix 8 for the regis-
ter settings after RESET is applied.
PROGRESSIVE SCAN INPUT
It is possible to input data to the ADV7194 in progressive scan
format. For this purpose the input pins Y0/P10–Y9/P19, Cr0–Cr9,
Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data and 10-bit Cr
data. The data is clocked into the part at 27 MHz. The data
is then filtered and sinc corrected in an 2× Interpolation filter
and then output to three video DACs at 54 MHz (to interface to
a progressive scan monitor).
It is assumed that there is no color space conversion or any other
such operation to be performed on the incoming data. Thus if
these DAC outputs are to drive a TV, all relevant timing and
synchronization data should be contained in the incoming digital
Y data. An FPGA can be used to achieve this.
The block diagram below shows a possible configuration for
progressive scan mode using the ADV7194.
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
–50
–60
–70
0
0
0
0
5
5
10
10
FREQUENCY – MHz
FREQUENCY – MHz
15
15
20
20
25
25
30
30