ADV7194KST Analog Devices Inc, ADV7194KST Datasheet - Page 31

• Manufacturer Part Number: ADV7194KST
• Description: IC ENCODER VIDEO EXT-10 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7194KST

• Rohs Status: RoHS non-compliant
• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• For Use With: EVAL-ADV7194EB - BOARD EVAL FOR ADV7194
• Lead Free Status / RoHS Status: Not Compliant

MODE REGISTER 2
MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 57 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION
RGB/YUV Control (MR20)
This bit enables the output from the DACs to be set to YUV or
RGB output video standard.
DAC Output Control (MR21)
This bit controls the output from DACs A, B, and C. When this
bit is set to 1, Composite, Luma and Chroma Signals are output
from DACs A, B and C (respectively). When this bit is set to 0,
RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC out-
put configurations is shown below.
Pedestal Control (MR23)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid when the device
is configured in PAL mode.
Square Pixel Control (MR24)
This bit is used to setup square pixel mode. This is available in
Slave Mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied. Square
pixel operation is not available in 4× Oversampling mode.
MR22
0
0
0
0
1
1
1
1
NOTE
In Progressive Scan Mode (MR80, 1) the DAC output configuration is stated in the brackets.
MR21
0
0
1
1
0
0
1
1
MR27
MR20
0
1
0
1
0
1
0
1
0
1
SLEEP MODE
CONTROL
DISABLE
ENABLE
MR27
MR26
VALID CONTROL
0
1
PIXEL DATA
DAC A
G (Y)
Y (Y)
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
DISABLE
ENABLE
MR26
MR25
STANDARD I
0
1
Table V. DAC Output Configuration
CONTROL
DISABLE
ENABLE
MR25
MR24
DAC B
B (Pb)
U (Pb)
LUMA
LUMA
B (Pb)
U (Pb)
LUMA
LUMA
2
SQUARE PIXEL
0
1
C
CONTROL
DISABLE
ENABLE
MR24
MR23
0
1
PEDESTAL
CONTROL
PEDESTAL OFF
PEDESTAL ON
Standard I
This bit controls the video standard used by the ADV7194.
When this bit is set to 1 the video standard is as programmed in
Mode Register 0 (Output Video Standard Selection). When it is
set to 0, the ADV7194 is forced into the standard selected by
the NTSC_PAL pin. When NTSC_PAL is low the standard is
NTSC, when the NTSC_PAL pin is high, the standard is PAL.
Pixel Data Valid Control (MR26)
After resetting the device this bit has the value 0 and the pixel
data input to the encoder is blanked such that a black screen is
output from the DACs. The ADV7194 will be set to Master
Mode timing. When this bit is set to 1 by the user (via the I
pixel data passes to the pins and the encoder reverts to the tim-
ing mode defined by Timing Mode Register 0.
Sleep Mode Control (MR27)
When this bit is set (1), Sleep Mode is enabled. With this mode
enabled the ADV7194 current consumption is reduced to typically
less than 0.1 mA. The I
from when the ADV7194 is in Sleep Mode.
When the device is in Sleep Mode and 0 is written to MR27, the
ADV7194 will come out of Sleep Mode and resume normal
operation. Also, if a RESET is applied during Sleep Mode the
ADV7194 will come out of Sleep Mode and resume normal
operation.
For this to operate, Power up in Sleep Mode control has to be
enabled (MR60 is set to a Logic 1), otherwise Sleep Mode is
controlled by the PAL_NTSC and SCRESET/RTC/TR pins.
MR23
DAC C
R (Pr)
V (Pr)
CHROMA
CHROMA
R (Pr)
V (Pr)
CHROMA
CHROMA
MR22
SCART ENABLE
0
1
CONTROL
DISABLE
ENABLE
MR22
2
C Control (MR25)
MR21
0
1
RGB/YUV/COMP
COMP/LUMA/CHROMA
DAC D
CVBS
CVBS
G (Y)
Y (Y)
G (Y)
Y (Y)
G (Y)
Y (Y)
DAC OUTPUT
MR21
CONTROL
2
MR20
C registers can be written to and read
0
1
CONTROL
RGB/YUV
RGB OUTPUT
YUV OUTPUT
MR20
B (Pb)
U (Pb)
B (Pb)
U (Pb)
DAC E
LUMA
LUMA
LUMA
LUMA
ADV7194
DAC F
CHROMA
CHROMA
R (Pr)
V (Pr)
CHROMA
CHROMA
R (Pr)
V (Pr)
2
C),