ADV7194KST Analog Devices Inc, ADV7194KST Datasheet - Page 32

• Manufacturer Part Number: ADV7194KST
• Description: IC ENCODER VIDEO EXT-10 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7194KST

• Rohs Status: RoHS non-compliant
• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• For Use With: EVAL-ADV7194EB - BOARD EVAL FOR ADV7194
• Lead Free Status / RoHS Status: Not Compliant

ADV7194
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)
Mode Register 3 is an 8-bit-wide register. Figure 58 shows
the various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30–MR31)
This bit is read only and indicates the revision of the device.
VBI_Open (MR32)
This bit determines whether or not data in the Vertical Blanking
Interval (VBI) is output to the analog outputs or blanked. Note
that this condition is also valid in Timing Slave Mode 0. For
further information see Vertical Blanking section.
Teletext Enable (MR33)
This bit must be set to 1 to enable teletext data insertion on
the TTX pin. Note: TTX functionality is shared with VSO and
CLAMP on Pin 62. CLAMP/VSO Select (MR77) and TTX
Input/CLAMP/VSO Output (MR76) have to be set accordingly.
Teletext Bit Request Mode Control (MR34)
This bit enables switching of the teletext request signal from a
continuous high signal (MR34 = 0) to a bitwise request signal
(MR34 = 1).
Closed Captioning Field Control (MR35–MR36)
These bits control the fields that closed captioning data is dis-
played on, closed captioning information can be displayed on
an odd field, even field or both fields.
Reserved (MR37)
A Logic 0 must be written to this bit.
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Mode Register 4 is an 8-bit-wide register. Figure 59 shows
the various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
VSYNC_3H Control (MR40)
When this bit is enabled (1) in Slave Mode, it is possible to
drive the VSYNC input low for 2.5 lines in PAL mode and
three lines in NTSC mode. When this bit is enabled in Master
Mode the ADV7194 outputs an active low VSYNC signal for
three lines in NTSC mode and 2.5 lines in PAL mode.
ZERO MUST BE
WRITTEN TO
THIS BIT
MR37
MR37
MR36 MR35
0
0
1
1
CLOSED CAPTIONING
MR36
0
1
0
1
FIELD CONTROL
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
MR35
MR34
TTX BIT REQUEST
MODE CONTROL
0
1
DISABLE
ENABLE
MR34
MR33
0
1
TELETEXT
ENABLE
DISABLE
ENABLE
Genlock Control (MR41–MR42)
These bits control the Genlock feature and timing reset of the
ADV7194 Setting MR41 and MR42 to Logic 0 disables the
SCRESET/RTC/TR pin and allows the ADV7194 to operate in
normal mode.
1. By setting MR41 to zero and MR42 to one, a timing reset is
2. If MR41 is set to one and MR42 is set to zero, the SCRESET/
3. If MR41 is set to one and MR42 is set to one, the SCRESET/
Active Video Line Duration Control (MR43)
This bit switches between two active video line durations. A zero
selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one
selects ITU-R BT. 470 standard for active video duration (710
pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)
This bit enables the color information to be switched on and off
the chroma, color component, composite video outputs.
Burst Control (MR45)
This bit enables the color burst to be switched on and off the
chroma and composite video outputs.
Color Bar Control (MR46)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7194 is configured in a
Master Timing mode. The output pins VSYNC, HSYNC and
BLANK are three-state during color bar mode.
Interlaced Mode Control (MR47)
This bit is used to setup the output to interlaced or noninterlaced
mode.
MR33
applied, resetting the horizontal and vertical counters. This
has the effect of resetting the Field Count to Field 0.
If the SCRESET/RTC/TR pin is held high, the counters
will remain reset. Once the pin is released the counters will
commence counting again. For correct counter reset, the
SCRESET/RTC/TR pin has to remain high for at least
37 ns (one clock cycle at 27 MHz).
RTC/TR pin is configured as a subcarrier reset input and
the subcarrier phase will reset to Field 0 whenever a low-to-
high transition is detected on the SCRESET/RTC/TR pin
(SCH phase resets at the start of the next field).
RTC/TR pin is configured as a real time control input and
the ADV7194 can be used to lock to an external video source
working in RTC mode. See Figure 37.
MR32
0
1
VBI OPEN
DISABLE
ENABLE
MR32
MR31
RESERVED FOR
REVISION CODE
MR31 MR30
MR30