ADV7184BSTZ Analog Devices Inc, ADV7184BSTZ Datasheet - Page 86

• Manufacturer Part Number: ADV7184BSTZ
• Description: IC DECODER VID SDTV MULTI 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7184BSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 10bit
• Adc Sample Rate: 54MSPS
• Power Dissipation Pd: 550mW
• No. Of Input Channels: 12
• Supply Voltage Range: 1.65V To 2V, 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Tv /: RoHS Compliant
• Input Format: Analogue
• Output Format: Digital
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7184
Address
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
Register
Default Value Y
Default Value C
Analog Devices
Control
Power Management
Status Register 1
(Read Only)
IDENT (Read Only)
Status Register 2
(Read Only)
Status Register 3
(Read only)
Brightness Register
Hue Register
Bit Description
BRI [7:0]. These bits control the brightness of
the video signal.
HUE [7:0]. These bits contain the value for the
color hue adjustment.
DEF_VAL_EN. Default value enable.
DEF_VAL_AUTO_EN. Default value.
DEF_Y [5:0]. Default value Y. These bits hold
the Y default value.
DEF_C [7:0]. Default value C. The Cr and Cb
default values are defined in these bits.
Reserved.
SUB_USR_EN. This bit enables the user to
access the user sub map.
Reserved.
Reserved.
FB_PWRDN.
PDBP. Power-down bit priority. This bit selects
between the PWRDN bit and the PWRDN pin.
Reserved.
PWRDN. Power-down. This bit places the
decoder in full power-down mode.
Reserved.
RES. Chip Reset. This bit loads all I
default values.
IN_LOCK.
LOST_LOCK.
FSC_LOCK.
FOLLOW_PW.
AD_RESULT [2:0]. Autodetection result. These
bits report the standard of the input video.
COL_KILL.
IDENT [7:0]. These bits provide identification
on the revision of the part.
MVCS DET.
MVCS T3.
MV_PS DET.
MV_AGC DET.
LL_NSTD.
FSC_NSTD.
Reserved.
INST_HLOCK.
GEMD.
SD_OP_50Hz.
CVBS.
2
C bits with
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7 6 5 4 3 2 1 0 Comments
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 1 1 0 1
0 1 1 1 1 1 0 0 Cr [7:0] = {DEF_C [7:4], 0, 0, 0, 0}
0 0
0
1
x
x x x x x x x x
x x
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
0
1
x
0 0 0 0 0 Set as default
0 0
x
Bit
x
x
x
1
0
1
x
x
x
0
1
0
1
x
x
x
0 Free-run mode dependent on
1 Force free-run mode on and
0 Set to default
x 1 = in lock (now)
x MV color striping detected
x 1 = horizontal lock achieved
DEF_VAL_AUTO_EN
output blue screen
Disable free-run mode
Enable automatic free-run mode
(blue screen)
Y [7:0] = {DEF_Y [5:0], 0, 0}
Cb [7:0] = {DEF_C [3:0], 0, 0, 0, 0}
Access user map
Access user sub map
Set as default
FB input operational
FB input in power-saving mode
Chip power-down controlled by pin
Bit has priority (pin disregarded)
Set to default
System functional
Powered down
Set to default
Normal operation
Start reset sequence
1 = lost lock (since last read)
1 = F
1 = peak white AGC mode active
NTSM M/J
NTSC 443
PAL M
PAL 60
PAL B/G/H/I/D
SECAM
PAL Combination N
SECAM 525
1 = color kill is active
MV color striping type
MV pseudosync detected
MV AGC pulses detected
Nonstandard line length
F
1 = Gemstar data detected
SD field rate detect
Result of composite/S-video
autodetection
SC
frequency nonstandard
SC
lock (now)
Notes
0x00 = 0 mV.
0x7F = +204 mV.
0x80 = −204 mV.
Hue range = −90° to +90°.
When lock is lost, free-run mode can
be enabled to output stable timing,
clock, and a set color.
Default Y value output in free-run
mode.
Default Cb/Cr value output in free-run
mode. Default values give blue screen
output.
See
This bit must be set to 1 for the PWRDN
bit to power down the part.
The PDBP bit must be set to 1 for the
PWRDN bit to power down the part
(see PDBP, 0x0F Bit 2).
Executing reset takes approximately
2 ms. This bit is self-clearing.
Provides information about the
internal status of the decoder.
Detected standard.
Color kill.
1 = detected.
0 = Type 2; 1 = Type 3.
1 = detected.
1 = detected.
1 = detected.
1 = detected.
Unfiltered.
When the GEMD bit goes high, it
remains high until the end of the
active video lines in that field.
0 = SD 60 Hz detected;
1 = SD 50 Hz detected.
0 = Y/C; 1 = CVBS.
Figure 48
.