ADV7184BSTZ Analog Devices Inc, ADV7184BSTZ Datasheet - Page 46

• Manufacturer Part Number: ADV7184BSTZ
• Description: IC DECODER VID SDTV MULTI 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7184BSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 10bit
• Adc Sample Rate: 54MSPS
• Power Dissipation Pd: 550mW
• No. Of Input Channels: 12
• Supply Voltage Range: 1.65V To 2V, 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Tv /: RoHS Compliant
• Input Format: Analogue
• Output Format: Digital
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7184
Table 61. HS Timing Parameters (see Figure 26)
Standard
NTSC
NTSC Square
PAL
HSE [10:0] HS End, Address 0x34 [2:0], Address 0x36 [7:0]
The position of this edge is controlled by placing a binary
number into HSE [10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 26). HSE is set to
00000000000, which is 0 LLC1 clock cycles from Count [0].
The default value of HSE [10:0] is 000, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.
For example,
•
•
To move 20 LLC1s away from active video is equal to subtracting
20 from 1716 and adding the result in binary to both HSB [10:0]
and HSE [10:0].
PHS Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit.
0 (default)—HS is active high.
1—HS is active low.
PIXEL
LLC1
BUS
HS
Pixel
To shift the HS toward active video by 20 LLC1s, add
20 LLC1s to both HSB and HSE, that is, HSB [10:0] =
[00000010110] and HSE [10:0] = [00000010100].
To shift the HS away from active video by 20 LLC1s, add
1696 LLC1s to both HSB and HSE (for NTSC), that is, HSB
[10:0] = [11010100010] and HSE [10:0] = [11010100000].
The number 1696 is derived from the NTSC total number
of pixels = 1716.
ACTIVE
VIDEO
D
Cr
E
Y
HS Begin Adjust
(HSB [10:0]) (Default)
00000000010
00000000010
00000000010
FF
00
4 LLC1
EAV
00
HSE[10:0]
XY
80
HS End Adjust
(HSE [10:0]) (Default)
00000000000
00000000000
00000000000
10
HSB[10:0]
80
10
H BLANK
80
Rev. A | Page 46 of 112
Figure 26. HS Timing
10
C
HS to Active Video
(LLC1 Clock Cycles)
(C in Figure 26) (Default)
272
276
284
Characteristics
VS and FIELD Configuration
The following controls allow the user to configure the behavior
of the VS and FIELD output pins and to generate the following
embedded AV codes:
•
•
•
•
•
•
•
•
•
•
•
•
•
FF
ADV encoder-compatible signals via NEWAVMODE
PVS, PF
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
For NTSC control
For PAL control
E
NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG [4:0]
NVENDDELO, NVENDDELE, NVENDSIGN, NVEND [4:0]
NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG [4:0]
PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG [4:0]
PVENDDELO, PVENDDELE, PVENDSIGN, PVEND [4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG [4:0]
00
SAV
00
XY
Active Video
Samples/Line
(D in Figure 26)
720Y + 720C = 1440
640Y + 640C = 1280
720Y + 720C = 1440
Cb
Y
Cr
ACTIVE VIDEO
Y
D
Cb
Y
Total LLC1
Clock Cycles
(E in Figure 26)
1716
1560
1728
Cr