ADV7180BCPZ Analog Devices Inc, ADV7180BCPZ Datasheet - Page 48

• Manufacturer Part Number: ADV7180BCPZ
• Description: IC VIDEO DECODER SDTV 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180BCPZ

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Resolution (bits): 10bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 57.27MSPS
• Power Dissipation Pd: 250mW
• No. Of Input Channels: 3
• Supply Voltage Range: 1.71V To 1.89V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7180
NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field,
Address 0xE5[7]
When NVBEGDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1 delays VSYNC going high on an odd
field by a line relative to NVBEG.
NVBEGDELE, NTSC VSYNC Begin Delay on Even Field,
Address 0xE5[6]
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays VSYNC going high on an
even field by a line relative to NVBEG.
NVBEGSIGN, NTSC VSYNC Begin Sign, Address 0xE5[5]
Setting NVBEGSIGN to 0 delays the start of VSYNC. Set for
user manual programming.
Setting NVBEGSIGN to 1 (default) advances the start of
VSYNC (not recommended for user programming).
NVBEG[4:0], NTSC VSYNC Begin, Address 0xE5[4:0]
The default value of NVBEG is 00101, indicating the NTSC
VSYNC begin position.
NOT VALID FOR USER
PROGRAMMING
VSYNC BY NVBEG[4:0]
ADVANCE BEGIN OF
ADVANCE BY
NVBEGDELO
ADDITIONAL
DELAY BY
0.5 LINE
VSBHO
1 LINE
YES
1
1
Figure 38. NTSC VSYNC Begin
1
VSYNC BEGIN
0
0
NVBEGSIGN
ODD FIELD?
0
0
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
ADVANCE BY
NVBEGDELE
ADDITIONAL
DELAY BY
0
0.5 LINE
VSBHE
1 LINE
NO
1
1
Rev. F | Page 48 of 116
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC signal on the VS pin are modified.
NVENDDELO, NTSC VSYNC End Delay on Odd Field,
Address 0xE6[7]
When NVENDDELO is 0 (default), there is no delay.
Setting NVENDDELO to 1 delays VSYNC from going low on
an odd field by a line relative to NVEND.
NVENDDELE, NTSC VSYNC End Delay on Even Field,
Address 0xE6[6]
When NVENDDELE is set to 0 (default), there is no delay.
Setting NVENDDELE to 1 delays VSYNC from going low on an
even field by a line relative to NVEND.
NVENDSIGN, NTSC VSYNC End Sign, Address 0xE6[5]
Setting NVENDSIGN to 0 (default) delays the end of VSYNC.
Set for user manual programming.
Setting NVENDSIGN to 1 advances the end of VSYNC (not
recommended for user programming).
NOT VALID FOR USER
PROGRAMMING
VSYNC BY NVEND[4:0]
ADVANCE END OF
ADVANCE BY
NVENDDELO
ADDITIONAL
DELAY BY
0.5 LINE
VSEHO
1 LINE
YES
1
1
Figure 39. NTSC VSYNC End
1
0
0
NVENDSIGN
ODD FIELD?
VSYNC END
0
0
DELAY END OF VSYNC
BY NVEND[4:0]
ADVANCE BY
NVENDDELE
ADDITIONAL
DELAY BY
0
0.5 LINE
VSEHE
1 LINE
NO
1
1