ADV7180BCPZ Analog Devices Inc, ADV7180BCPZ Datasheet - Page 103

• Manufacturer Part Number: ADV7180BCPZ
• Description: IC VIDEO DECODER SDTV 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180BCPZ

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Resolution (bits): 10bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 57.27MSPS
• Power Dissipation Pd: 250mW
• No. Of Input Channels: 3
• Supply Voltage Range: 1.71V To 1.89V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Address Register
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7D
0x7E
0x7F
0x84
0x85
VDP_LINE_01E
VDP_LINE_01F
VDP_LINE_020
VDP_LINE_021
VDP_STATUS
(read only)
VDP_STATUS_CLEAR
(write only)
VDP_CCAP_DATA_0
(read only)
VDP_CCAP_DATA_1
(read only)
VDP_CGMS_WSS_DATA_0
(read only)
VDP_CGMS_WSS_DATA_1
(read only)
VDP_CGMS_WSS_DATA_2
(read only)
VDP_GS_VPS_PDC_UTC_0
(read only)
VDP_GS_VPS_PDC_UTC_1
(read only)
User Sub Map
Bit Description
VBI_DATA_P334_N282[3:0]
VBI_DATA_P21_N19[3:0]
VBI_DATA_P335_N283[3:0]
VBI_DATA_P22_N20[3:0]
VBI_DATA_P336_N284[3:0]
VBI_DATA_P23_N21[3:0]
VBI_DATA_P337_N285[3:0]
VBI_DATA_P24_N22[3:0]
CC_AVL
CC_EVEN_FIELD
CGMS_WSS_AVL
Reserved
GS_PDC_VPS_UTC_AVL
GS_DATA_TYPE
VITC_AVL
TTXT_AVL
CC_CLEAR
Reserved
CGMS_WSS_CLEAR
Reserved
GS_PDC_VPS_UTC_CLEAR
Reserved
VITC_CLEAR
Reserved
CCAP_BYTE_1[7:0]
CCAP_BYTE_2[7:0]
CGMS_CRC[5:2]
Reserved
CGMS_WSS[13:8]
CGMS_CRC[1:0]
CGMS_WSS[7:0]
GS_VPS_PDC_UTC_BYTE_0[7:0]
GS_VPS_PDC_UTC_BYTE_1[7:0]
Rev. F | Page 103 of 116
7 6 5 4 3 2 1 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0
1
0
x x x x x x x x
x x x x x x x x
0 0 0 0
x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
Bit
0
1
0
1
(Shading Indicates
Default State)
0
1
0
x x x x x x
0
1
0
1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0
0
x x x x
0
1
0
1
0
1
0
0
1
0
1
Comments
Sets VBI standard to be decoded from
Line 334 (PAL), Line 282 (NTSC)
Sets VBI standard to be decoded from
Line 21 (PAL), Line 19 (NTSC)
Sets VBI standard to be decoded from
Line 335 (PAL), Line 283 (NTSC)
Sets VBI standard to be decoded from
Line 22 (PAL), Line 20 (NTSC)
Sets VBI standard to be decoded from
Line 336 (PAL), Line 284 (NTSC)
Sets VBI standard to be decoded from
Line 23 (PAL), Line 21 (NTSC)
Sets VBI standard to be decoded from
Line 337 (PAL), Line 285 (NTSC)
Sets VBI standard to be decoded from
Line 24 (PAL), Line 22 (NTSC)
Closed captioning not detected
Closed captioning detected
Closed captioning decoded from
odd field
Closed captioning decoded from
even field
CGMS/WSS not detected
CGMS/WSS detected
GS/PDC/VPS/UTC not detected
GS/PDC/VPS/UTC detected
Gemstar_1× detected
Gemstar_2× detected
VITC not detected
VITC detected
Teletext not detected
Teletext detected
Does not reinitialize the CCAP readback
registers
Reinitializes the CCAP readback registers
Does not reinitialize the CGMS/WSS
readback registers
Reinitializes the CGMS/WSS readback
registers
Does not reinitialize the GS/PDC/VPS/
UTC readback registers
Refreshes the GS/PDC/VPS/UTC
readback registers
Does not reinitialize the VITC readback
registers
Reinitializes the VITC readback registers
Decoded Byte 1 of CCAP
Decoded Byte 2 of CCAP
Decoded CRC sequence for CGMS
Decoded CGMS/WSS data
Decoded CRC sequence for CGMS
Decoded CGMS/WSS data
Decoded Gemstar/VPS/PDC/UTC data
Decoded Gemstar/VPS/PDC/UTC data
CC_CLEAR resets the
Notes
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
MAN_LINE_PGM must be
set to 1 for these bits to
be effective
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
CC_AVL bit
CGMS_WSS_CLEAR resets
the CGMS_WSS_AVL bit
GS_PDC_VPS_UTC_CLEAR
resets the
GS_PDC_VPS_UTC_AVL
bit
VITC_CLEAR resets the
VITC_AVL bit
This is a self-clearing bit
This is a self-clearing bit
This is a self-clearing bit
This is a self-clearing bit
ADV7180