WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 73

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
Table 50
Table 51
Cortina Systems
Configuration Register - Address 16, Hex 10 (Sheet 2 of 2)
Status Register #2 - Address 17, Hex 11 (Sheet 1 of 2)
®
1. R/W = Read /Write
1. RO = Read Only. R/W = Read/Write
16.4:3
17.15
17.14
17.13
17.12
17.10
17.11
16.8
16.7
16.6
16.5
16.2
16.1
16.0
17.9
17.8
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Bit
Bit
TP Loopback
(10BASE-T)
CRS Select
(10BASE-T)
Reserved
PRE_EN
Reserved
Reserved
Alternate NP feature
Reserved
Reserved
10/100 Mode
Transmit Status
Receive Status
Collision Status
Link
Duplex Mode
Auto-Negotiation
Name
Name
0 = Normal operation
1 = Disable TP loopback during half-duplex
0 = Normal Operation
1 = CRS deassert extends to RX_DV deassert
Write as ‘0’. Ignore on Read.
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
Note:
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
0 = Disable alternate auto negotiate next page
1 = Enable alternate auto negotiate next page
Note:
Write as ‘0’. Ignore on Read.
Always 0.
0 = LXT972M PHY is not operating 100BASE-TX
1 = LXT972M PHY is operating in 100BASE-TX
0 = LXT972M PHY is not transmitting a packet.
1 = LXT972M PHY is transmitting a packet.
0 = LXT972M PHY is not receiving a packet.
1 = LXT972M PHY is receiving a packet.
0 = No collision.
1 = Collision is occurring.
0 = Link is down.
1 = Link is up.
0 = Half-duplex.
1 = Full-duplex.
0 = LXT972M PHY is in manual mode.
1 = LXT972M PHY is in auto-negotiation mode.
operation
CRS is asserted.
feature.
feature.
mode.
mode.
Preamble is always enabled in 100 Mbps
operation.
This bit enables or disables the register
bit 6.5 capability.
Description
Description
Product-Specific Registers
9.0 Register Definitions -
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
1
1
Default
Default
Page 73
00
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0