WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 34

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
Figure 10
5.6.7.1
5.6.7.2
Note:
Cortina Systems
Loopback Paths
Operational Loopback
Internal Digital Loopback (Test Loopback)
A test loopback function is provided for diagnostic testing of the LXT972M PHY. During
test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC
is internally looped back by the LXT972M PHY and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled
by setting the following register bits:
Parallel detection can resolve the PHY configuration.
®
• Operational loopback is provided for 10 Mbps half-duplex links when register bit 16.8
• Operational loopback is not provided for 100 Mbps links, full-duplex links, or when
• register bit 0.14 = 1 (Setting to enable loopback mode)
• register bit 0.8 = 1 (Setting for full-duplex mode)
• register bit 0.12 = 0 (Disable auto-negotiation)
LXT972M Single-Port 10/100 Mbps PHY Transceiver
= 0. Data that the MAC (TXData) transmits loops back on the receive side of the MII
(RXData).
Register 16.8 = 1.
MII
LXT97x PHY
Loopback
Operational
Loopback
10T
Digital
Block
Test Loopback
Loopback
100X
Analog
Block
5.6 MII Operation
B3485-02
Driver
TX
Page 34