KS8721B TR Micrel Inc, KS8721B TR Datasheet - Page 25

• Manufacturer Part Number: KS8721B TR
• Description: IC TXRX PHY 10/100 2.5V 48SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KS8721B TR

• Number Of Drivers/receivers: 1/1
• Protocol: MII, RMII
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 576-1006 - BOARD EVAL EXPERIMENT KS8721B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: KS8721BTR

Symbol
Symbol
t
t
t
t
t
t
t
t
March 2006
SU1
SU2
HD1
HD2
HD3
CRS1
CRS2
LAT
Parameter
Parameter
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXER Hold After TXC High
TXER Hold After TXC High
TXER Hold After TXC High
TXER Hold After TXC High
TXER Hold After TXC High
TXER Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN High to TX+/TX– Output (TX Latency)
TXEN High to TX+/TX– Output (TX Latency)
TXEN High to TX+/TX– Output (TX Latency)
TXEN High to TX+/TX– Output (TX Latency)
TXEN High to TX+/TX– Output (TX Latency)
TXEN High to TX+/TX– Output (TX Latency)
TXC
TXEN
TXD[3:0],
TXER
CRS
TX+/TX-
Table 3. 100BaseT MII Transmit Timing Parameters
Figure 5. 100BaseT MII Transmit Timing
t
SU2
t
Data
In
SU1
t
CRS1
t
LAT
t
t
HD2
HD1
Symb ol
Out
25
t
CRS2
Min
Min
Min
Min
10
10
10
10
10
10
10
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Typ
Typ
Typ
Typ
4
4
4
4
4
4
4
4
4
4
4
4
9
9
9
9
9
9
Max
Max
Max
Max
M9999-030106
Units
Units
Units
Units
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns