KS8721B TR Micrel Inc, KS8721B TR Datasheet - Page 24

• Manufacturer Part Number: KS8721B TR
• Description: IC TXRX PHY 10/100 2.5V 48SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KS8721B TR

• Number Of Drivers/receivers: 1/1
• Protocol: MII, RMII
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 576-1006 - BOARD EVAL EXPERIMENT KS8721B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: KS8721BTR

Timing Diagrams
Symbol
Symbol
t
t
t
t
t
t
t
t
t
M9999-030106
SU1
SU2
HD1
HD2
CRS1
CRS2
LAT
SQE
SQEP
Parameter
Parameter
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXD [3:0] Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXEN Set-Up to TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXD [3:0] Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN Hold After TXC High
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN High to CRS Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN Low to CRS De-Asserted Latency
TXEN High to TXP/TXM Output (TX Latency)
TXEN High to TXP/TXM Output (TX Latency)
TXEN High to TXP/TXM Output (TX Latency)
TXEN High to TXP/TXM Output (TX Latency)
TXEN High to TXP/TXM Output (TX Latency)
TXEN High to TXP/TXM Output (TX Latency)
COL (SQE) Delay Aftter TXEN Ae-Asserted
COL (SQE) Delay Aftter TXEN Ae-Asserted
COL (SQE) Delay Aftter TXEN Ae-Asserted
COL (SQE) Delay Aftter TXEN Ae-Asserted
COL (SQE) Delay Aftter TXEN Ae-Asserted
COL (SQE) Delay Aftter TXEN Ae-Asserted
COL (SQE) Pulse Duration
COL (SQE) Pulse Duration
COL (SQE) Pulse Duration
COL (SQE) Pulse Duration
COL (SQE) Pulse Duration
COL (SQE) Pulse Duration
SQE Timing
TXC
TXEN
TXD[3:0]
CRS
TXP/TXM
TXC
TXEN
COL
Table 2. 10BaseT MII Transmit Timing Parameters
t
SU2
t
SU1
Figure 4. 10BaseT MII Transmit Timing
t
LA T
t
CRS1
t
SQE
t
t
HD2
HD1
Valid
Data
24
t
SQEP
t
CRS2
Min
Min
Min
Min
10
10
10
10
10
10
10
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
Typ
Typ
Typ
Typ
2.5
2.5
2.5
2.5
2.5
2.5
1.0
1.0
1.0
1.0
1.0
1.0
4
4
4
4
4
4
8
8
8
8
8
8
4
4
4
4
4
4
Max
Max
Max
Max
March 2006
Units
Units
Units
Units
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
BT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs