KS8721B A4 Micrel Inc, KS8721B A4 Datasheet

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KS8721B A4

Manufacturer Part Number
KS8721B A4
Description
Manufacturer
Micrel Inc
Datasheet

Specifications of KS8721B A4

Lead Free Status / RoHS Status
Not Compliant
General Description
Operating at 2.5 volts to meet low voltage and low power
requirements, the KS8721B/BT is a 10BaseT/100BaseTX/FX
Physical Layer Transceiver, which provides an MII to transmit
and receive data. It contains the 10BaseT Physical Medium
Attachment (PMA), Physical Medium Dependent (PMD), and
Physical Coding Sub-layer (PCS) functions. Moreover, the
KS8721B/BT has on-chip 10BaseT output fi ltering, which
eliminates the need for external fi lters and allows a single
set of line magnetics to be used to meet requirements for
both 100BaseTX and 10BaseT.
The KS8721B/BT can automatically confi gure itself for 100
or 10 Mbps and full or half duplex operation, using on-chip
Auto-Negotiation algorithm. It is an ideal choice of physical
layer transceiver for 100BaseTX/10BaseT applications.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Functional Diagram
March 2006
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
TX+
TX-
RX+
RX-
XO
XI
Transmitter
PLL
Wander Correction
10BaseT
Receiver
MLT3 Decoder
Adaptive EQ
NRZI/NRZ
Base Line
Shaper
10/100
Pulse
MLT3 Encoder
NRZ/NRZI
Negotiation
PWRDWN
Recovery
Down or
Saving
Power
Clock
Auto
1
Features
• Single chip 100BaseTX/100BaseFX/10BaseT physical
• 2.5V CMOS design, power consumption <200mW (ex-
• Fully compliant to IEEE 802.3u standard
• Supports Media Independent Interface (MII) and
• Supports 10BaseT, 100BaseTX and 100BaseFX with
• Supports power down mode and power saving mode
• Confi gurable through MII serial management ports or via
• Supports auto-negotiation and manual selection for
• On-chip built-in analog front end fi ltering for both 100Ba-
2.5V 10/100BasTX/FX MII Physical Layer Transceiver
layer solution
cluding output driver current )
Reduced MII (RMII)
Far_End_Fault Detection
external control pins
10/100Mbps speed and full/half-duplex mode
seTX and 10BaseT
Manchester Encoder
Manchester Decoder
4B/5B Encoder
4B/5B Decoder
Parallel/Serial
Parallel/Serial
Serial/Parallel
Serial/Parallel
Descrambler
Scrambler
KS8721B/BT
KS8721B/BT
Rev. 2.3
Controller
Registers
Interface
MII/RMII
Driver
LED
and
CRS
MDIO
MDC
COL
TXD3
TXD2
TXD1
TXD0
TXER
TXC
TXEN
COL
RXD3
RXD2
RXD1
RXD0
RXER
RXDV
RXC
LINK
FDX
SPD
M9999-030106

Related parts for KS8721B A4

KS8721B A4 Summary of contents

Page 1

... The KS8721B/BT can automatically confi gure itself for 100 or 10 Mbps and full or half duplex operation, using on-chip Auto-Negotiation algorithm ideal choice of physical layer transceiver for 100BaseTX/10BaseT applications. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. ...

Page 2

Features (continued) • LED outputs for link, activity, full/half duplex, collision and speed • Supports back to back for media converter applications • Supports MDI/MDI-X auto crossover • 2.5V/3.3V tolerance on I/O • Commercial temperature range: 0°C ...

Page 3

Revision History Revision Date Revision Date Revision Date Summary of Changes Summary of Changes Summary of Changes 1.0 1.0 1.0 1.0 2/29/02 2/29/02 2/29/02 2/29/02 Document Origination (Preliminary) Document Origination (Preliminary) Document Origination (Preliminary) Document Origination (Preliminary) 2.0 2.0 2.0 ...

Page 4

... FX Mode ....................................................................................................................................................16 Media Converter Option ........................................................................................................................................16 Register Map ............................................................................................................................................................17 Register 0h: Basic Conrol .....................................................................................................................................17 Register 1h: Basic Status .....................................................................................................................................18 Register 2h: PHY Identifi ................................................................................................................................18 Register 3h: PHY Identifi ................................................................................................................................18 Register 4h: Auto-Negotiation Advertisement .......................................................................................................18 Register 5h: Auto-Negotiation Link Partner Ability ................................................................................................18 Register 6h: Auto-Negotiation Expansion .............................................................................................................19 Register 7h: Auto-Negotiation Next Page .............................................................................................................19 Register 8h: Link Partner Next Page Ability .........................................................................................................19 Register 15h: RXER Counter Register 15h: RXER Counter ...

Page 5

Absolute Maximum Ratings .......................................................................................................................................22 Operating Ratings .......................................................................................................................................................22 Electrical Characteristics ...........................................................................................................................................22 Timing Diagrams .........................................................................................................................................................24 Selection of Isolation Transformers ..........................................................................................................................30 Selection of Reference Crystals ................................................................................................................................30 Package Outline and Dimensions .............................................................................................................................31 March 2006 5 M9999-030106 ...

Page 6

... MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] during reset. See during reset. See during reset. See “ ...

Page 7

... Pin Function Pin Function Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up /reset. See “ ...

Page 8

Pin Number Pin Number Pin Number Pin Name Pin Name Pin Name Type Type Type REXT REXT REXT REXT REXT VDDRCV VDDRCV VDDRCV VDDRCV VDDRCV ...

Page 9

... PD = strap pin pull-down Note 3. Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset rcommended that an external pull down via 1kΩ resistor be used in these applications to augment the 8721's internal pull down. March 2006 ...

Page 10

... SSOP (SM) M9999-030106 48 RST# 47 VDDPLL GND 43 GND 42 VDDTX 41 TX+ 40 TX- 39 GND 38 VDDRCV 37 REXT MDIO 36 GND MDC RXD3/PHYAD1 35 GND RXD2/PHYAD2 34 FXSD/FXEN RXD1/PHYAD3 RXD0/PHYAD4 33 RX+ VDDIO GND 32 RX- RXDV/PCS_LPBK 31 VDDRX RXC RXER/ISO 30 PD# GND 29 LED3/NWAYEN 28 LED2/DUPLEX 27 LED1/SPD100 26 LED0/TEST 25 INT#/PHYAD0 GND GND 3 34 ...

Page 11

Introduction 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, NRZ to NRZI conversion, MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion, which converts the 25MHz, 4-bit nibbles into a 125 MHz serial ...

Page 12

... Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721B/BT. The MDIO interface consists of the following: • A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT) • A specifi c protocol that runs across the above-mentioned physical connection and it also allows one controller to communicate with multiple KS8721B/BT devices ...

Page 13

... RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device. Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single IC. ...

Page 14

... MII only supports chip-to-chip connections on a PCB, SQE functionality is not required. RX_ER The PHY shall provide RX_ER as an output according to the rules specifi IEEE 802.3u [2] (see Clause 24, Figure 24 Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was detected somewhere in the frame presently being transferred from the PHY ...

Page 15

... The assignment of pin-outs for a 10/100 BASE-T crossover function cable is shown below. This feature can eliminate the confusion in real applications so both straight cable and crossover cable can be used. This feature is controlled by register 1f:13. See “Register 1fh–100BaseTX PHY Controller” section for details. 10/100 BASE-T ...

Page 16

Power Management The KS8721B/BT offers the following modes for power management: • Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# Low. • Power Saving Mode: This mode can be disabled ...

Page 17

... PHY from MII and TX+/TX electrical isolation of PHY from MII and TX+/TX electrical isolation of PHY from MII and TX+/TX electrical isolation of PHY from MII and TX+/TX electrical isolation of PHY from MII and TX+/TX- ...

Page 18

... Extended Capability Extended Capability Extended Capability Extended Capability Extended Capability Extended Capability Register 2h - PHY Identifi Register 2h - PHY Identifi 2.15:0 2.15:0 2.15:0 2.15:0 2.15:0 2.15:0 PHY ID Number PHY ID Number PHY ID Number PHY ID Number PHY ID Number PHY ID Number Register 3h - PHY Identifi ...

Page 19

Address Address Address Address Name Name Name Name 5.11:10 5.11:10 5.11:10 5.11:10 5.11:10 5.11:10 Pause Pause Pause Pause Pause Pause 5.9 5.9 5.9 5.9 5.9 100 BaseT4 100 BaseT4 100 BaseT4 100 BaseT4 100 BaseT4 5.8 5.8 5.8 5.8 5.8 ...

Page 20

... Remote Fault Interrupt Remote Fault Interrupt 1b.0 1b.0 1b.0 1b.0 1b.0 1b.0 Link Up Interrupt Link Up Interrupt Link Up Interrupt Link Up Interrupt Link Up Interrupt Link Up Interrupt Register 1fh - 100BaseTX PHY Controller 1f.15:14 1f.15:14 1f.15:14 Reserved Reserved Reserved 1f:13 1f:13 1f:13 1f:13 1f:13 1f:13 Pairswap Disable ...

Page 21

... PHY in isolate mode not isolated 1 = PHY in isolate mode not isolated 1 = PHY in isolate mode not isolated 1 = PHY in isolate mode not isolated 1 = PHY in isolate mode not isolated [001] = 10BaseT half duplex [001] = 10BaseT half duplex ...

Page 22

Absolute Maximum Ratings Supply Voltage ( DDC DD_PLL DD_TX DD_RCV V ) ....................................................–0.5V to +3.0V DD_RX DD_RX DD_RX DD_RX DD_RX ( ......................................................–0.5V to +4.0V DDIO Input Voltage ................................................–0.5V to +4.0V Output ...

Page 23

Symbol Symbol Symbol Symbol Symbol Symbol Symbol Parameter Parameter Parameter Parameter Parameter Parameter Parameter 10BaseTX Receive R RX+/RX– Differential RX+/RX– Differential RX+/RX– Differential RX+/RX– Differential RX+/RX– Differential RX+/RX– Differential IN Input Resistance Input Resistance Input Resistance Input Resistance V Squelch ...

Page 24

Timing Diagrams TXC TXEN TXD[3:0] CRS TXP/TXM SQE Timing TXC TXEN COL Symbol Symbol Parameter Parameter t TXD [3:0] Set-Up to TXC High TXD [3:0] Set-Up to TXC High TXD [3:0] Set-Up to TXC High TXD [3:0] Set-Up to TXC ...

Page 25

TXC TXEN TXD[3:0], TXER CRS TX+/TX- Symbol Symbol Parameter Parameter t TXD [3:0] Set-Up to TXC High TXD [3:0] Set-Up to TXC High TXD [3:0] Set-Up to TXC High TXD [3:0] Set-Up to TXC High TXD [3:0] Set-Up to TXC ...

Page 26

RX+/RX- CRS RXDV RXD[3:0] RXER RXC Symbol Symbol Parameter Parameter t RXC Period RXC Period RXC Period RXC Period RXC Period RXC Period P t RXC Pulse Width RXC Pulse Width RXC Pulse Width RXC Pulse Width RXC Pulse Width ...

Page 27

TX+/TX- TX+/TX- Figure 7. Auto-Negotiation/Fast Link Pulse Timing Symbol Symbol Parameter Parameter t FLP Burst to FLP Burst FLP Burst to FLP Burst FLP Burst to FLP Burst FLP Burst to FLP Burst FLP Burst to FLP Burst FLP Burst ...

Page 28

MDC MDI O (Into Ch ip) MDI O (Out of Chip) Symbol Symbol Parameter Parameter t MDC Period MDC Period MDC Period MDC Period MDC Period MDC Period P t MDIO Set-Up to MDC (MDIO as input) MDIO Set-Up to ...

Page 29

Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Symbol Parameter Parameter t Stable Supply Voltages to Reset High Stable Supply Voltages to Reset High Stable Supply Voltages to Reset High Stable Supply Voltages to Reset High Stable Supply ...

Page 30

Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer character- istics. Characteristics Name Characteristics Name ...

Page 31

Package Information March 2006 48-Pin SSOP (SM) 31 M9999-030106 ...

Page 32

... MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifi cations at any time without notifi cation to the customer. ...

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