DS26514GN+ Maxim Integrated Products, DS26514GN+ Datasheet - Page 60

• Manufacturer Part Number: DS26514GN+
• Description: IC TXRX T1/E1/J1 4PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26514GN+

• Number Of Drivers/receivers: 4/4
• Protocol: Ethernet
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.9.5.3 Legacy T1 Transmit FDL
It is recommended that the DS26514’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL.
Table 9-21. Registers Related to T1 Transmit FDL
Transmit FDL Register (T1TFDL)
Transmit Control Register 2 (T1.TCR2)
Transmit Latched Status Register 2 (TLS2)
Transmit Interrupt Mask Register 2 (TIM2)
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
When enabled with T1.TCR2.7, the transmit section will shift out into the T1 data stream, either the FDL (in the
ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL Register (T1TFDL).
When a new value is written to the T1TFDL, it will be multiplexed serially (LSB first) into the proper position in the
outgoing T1 data stream. After the full eight bits has been shifted out, the framer will signal the host controller that
the buffer is empty and that more data is needed by setting the TLS2.4 bit to a one. INTB will also toggle low if
enabled via TIM2.4. The user has 2ms to update the
old value in the
applied to the FDL data. It is strongly suggested that the HDLC controller be used for FDL messaging applications.
In the D4 framing mode, the framer uses the
the
T1TFDL
The
outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used.
9.9.5.4 Legacy T1 Receive FDL
It is recommended that the DS26514’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL.
Table 9-22. Registers Related to T1 Receive FDL
Receive FDL Register (T1RFDL)
Receive Latched Status Register 7(RLS7)
Receive Interrupt Mask Register 7(RIM7)
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL Register
(T1RFDL). Since the
external controller that the buffer has filled via the RLS7.2 bit. If enabled via RIM7.2, the INTB pin will toggle low
indicating that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note
that no zero destuffing is applied to the for the data provided through the
reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing
mode,
Rev: 101608
T1TFDL
T1TFDL
T1RFDL
register).
register must be programmed to 1Ch and T1.TCR2.7 should be set to 0 (source Fs data from the
register contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the
REGISTER
updates on multiframe boundaries and reports only the Fs bits.
REGISTER
T1TFDL
Table 9-21
Table 9-22
T1RFDL
register will be transmitted once again. Note that in this mode, no zero stuffing will be
shows the registers related to control of the transmit FDL.
shows the registers related to the receive FDL.
is 8 bits in length, it will fill up every 2ms (8 times 250μs). The framer will signal an
ADDRESSES
T1TFDL
FRAMER 1
ADDRESSES
0A6h
062h
096h
FRAMER 1
1A1h
162h
182h
191h
T1TFDL
register to insert the Fs framing pattern. To accomplish this
FDL code used to receive FDL.
Receive FDL full bit is in this register.
Mask bit for RFDL full.
with a new value. If the
FDL code used to insert transmit FDL.
Defines the source of the FDL.
Transmit FDL empty bit.
Mask bit for TFDL empty.
T1RFDL
DS26514 4-Port T1/E1/J1 Transceiver
FUNCTION
FUNCTION
register. The
T1TFDL
is not updated, the
T1RFDL
60 of 305
register