DS26514GN+ Maxim Integrated Products, DS26514GN+ Datasheet

DS26514GN+

Manufacturer Part Number

DS26514GN+

Description

IC TXRX T1/E1/J1 4PORT 256-CSBGA

Manufacturer

Maxim Integrated Products

Type

Transceiverr

Datasheet

1.DS26514GN.pdf (305 pages)

Specifications of DS26514GN+

Number Of Drivers/receivers

4/4

Protocol

Ethernet

Voltage - Supply

3.14 V ~ 3.47 V

Mounting Type

Surface Mount

Package / Case

256-CSBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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The DS26514 is a 4-port framer and line interface

unit (LIU) combination for T1, E1, J1 applications.

Each port is independently configurable, supporting

both long-haul and short-haul lines. The DS26514

single-chip transceiver (SCT) is software and pinout

compatible with the 8-port DS26518. It is nearly

software compatible with the DS26528 and its

derivatives.

Routers

Channel Service Units (CSUs)

Data Service Units (DSUs)

Muxes

Switches

Channel Banks

T1/E1 Test Equipment

+Denotes a lead-free/RoHS compliant package.

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about device

errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Rev: 101608

______________ General Description

___________________ Applications

______________ Functional Diagram

_____________ Ordering Information

DS26514GN

DS26514GN+

NETWORK

PART

T1/E1/J1

Transceiver

-40°C to +85°C

TEMP RANGE

T1/J1/E1

DS26514

PIN-PACKAGE

256 TE-CSBGA

BACKPLANE

TDM

4-Port T1/E1/J1 Transceiver

♦ Four Complete T1, E1, or J1 Long-Haul/

♦ Independent T1, E1, or J1 Selections for Each

♦ Fully Internal Impedance Match, No External

♦ Software-Selectable Transmit- and Receive-

♦ Hitless Protection Switching

♦ Crystal-Less Jitter Attenuators Can Be

♦ External Master Clock Can Be Multiple of

♦ Receive-Signal Level Indication from -2.5dB

♦ Transmit Open- and Short-Circuit Detection

♦ LIU LOS in Accordance with G.775, ETS 300

♦ Transmit Synchronizer

♦ Flexible Signaling Extraction and Insertion

♦ Alarm Detection and Insertion

♦ T1 Framing Formats of D4, SLC-96, and ESF

♦ J1 Support

♦ E1 G.704 and CRC-4 Multiframe

♦ T1-to-E1 Conversion

Features continued in Section 2.

_______________________ Features

Short-Haul Transceivers (LIU Plus Framer)

Transceiver

Resistor

Side Termination for 100Ω T1 Twisted Pair,

110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,

and 75Ω E1 Coaxial Applications

Selected for Transmit or Receive Path; Jitter

Attenuator Meets ETS CTR 12/13, ITU-T

G.736, G.742, G.823, and AT&T Pub 62411

2.048MHz or 1.544MHz for T1/J1 or E1

Operation; This Clock is Internally Adapted

for T1 or E1 Usage in the Host Mode

to -36dB in T1 Mode and -2.5dB to -44dB in E1

Mode in Approximate 2.5dB Increments

233, and T1.231

Using Either the System Interface or

Microprocessor Port

Maxim Integrated Products 1

DS26514

Related parts for DS26514GN+

DS26514GN+ Summary of contents

Page 1

... PART TEMP RANGE DS26514GN -40°C to +85°C DS26514GN+ -40°C to +85°C +Denotes a lead-free/RoHS compliant package. Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’ ...

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DETAILED DESCRIPTION.................................................................................................9 2. FEATURE HIGHLIGHTS ..................................................................................................10 2.1 G ......................................................................................................................................10 ENERAL 2 ............................................................................................................................10 INE NTERFACE 2 LOCK YNTHESIZERS 2 .....................................................................................................................10 ITTER TTENUATOR 2 ....................................................................................................................11 RAMER ORMATTER 2 ......................................................................................................................11 YSTEM NTERFACE ...

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Alarms .................................................................................................................................................. 65 9.9.9 Error Count Registers .......................................................................................................................... 67 9.9.10 DS0 Monitoring Function...................................................................................................................... 69 9.9.11 Transmit Per-Channel Idle Code Generation ...................................................................................... 70 9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 70 9.9.13 Per-Channel Loopback ........................................................................................................................ 70 9.9.14 E1 G.706 Intermediate CRC-4 ...

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T C HERMAL HARACTERISTICS 12 INE NTERFACE HARACTERISTICS 13. AC TIMING CHARACTERISTICS ..................................................................................285 13 ICROPROCESSOR 13.1.1 SPI Bus Mode .................................................................................................................................... 285 13.2 JTAG I T NTERFACE IMING 14. JTAG BOUNDARY SCAN AND TEST ACCESS ...

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Figure 7-1. Block Diagram ......................................................................................................................................... 18 Figure 7-2. Detailed Block Diagram........................................................................................................................... 19 Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 29 Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = ...

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Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 273 Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 274 Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 274 Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 275 Figure ...

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Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14 Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15 Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16 Table 8-1. Detailed Pin Descriptions ......................................................................................................................... 20 Table 9-1. CLKO Frequency Selection ...................................................................................................................... 32 Table 9-2. Reset Functions........................................................................................................................................ 33 ...

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Table 10-2. Global Register List .............................................................................................................................. 103 Table 10-3. Framer Register List ............................................................................................................................. 104 Table 10-4. LIU Register List ................................................................................................................................... 111 Table 10-5. BERT Register List ............................................................................................................................... 112 Table 10-6. HDLC-256 Register List........................................................................................................................ 113 Table 10-7. Global Register Bit Map........................................................................................................................ ...

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DETAILED DESCRIPTION The DS26514 is an 4-port monolithic device featuring independent transceivers that can be software configured for T1, E1 operation. Each transceiver is composed of a line interface unit, framer, two HDLC controllers, elastic store, and ...

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FEATURE HIGHLIGHTS 2.1 General 17mm x 17mm, 256-pin TE-CSBGA (1.00mm pitch) 3.3V supply with 5V tolerant inputs and outputs IEEE 1149.1 JTAG boundary scan Development support includes evaluation kit, driver source code, and reference designs 2.2 Line Interface Requires ...

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Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats D4 and ESF per T1.403 and expanded SLC-96 support (TR-TSY-008) E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe Transmit-side ...

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Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode User-selectable synthesized clock output 2.7 HDLC Controllers Two HDLC controller engines for each T1/E1 port HDLC-64: Independent 64-byte Rx and Tx buffers ...

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APPLICATIONS The DS26514 is useful in applications such as: Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment Rev: 101608 DS26514 4-Port T1/E1/J1 Transceiver 13 of 305 ...

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SPECIFICATIONS COMPLIANCE The DS26514 meets all the latest relevant telecommunications specifications. specifications and Table 4-2 provides the E1 specifications and relevant sections that are applicable to the DS26514. Table 4-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface ...

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Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-to- peak space voltage is ±0.237V; nominal pulse width is ...

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ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125μs T1 frame, there are 24 8-bit channels plus a framing bit assumed that the framing bit is ...

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MAJOR OPERATING MODES The DS26514 has two major modes of operation: T1 mode and E1 mode. The mode of operation for each LIU is configured in the LTRCR register. The mode of operation for each framer is configured in ...

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BLOCK DIAGRAMS Figure 7-1. Block Diagram DS26514 LIU #4 LIU #3 LIU #2 RTIP RRING LINE INTERFACE TTIP UNIT TRING x4 MICRO PROCESSOR INTERFACE CONTROLLER PORT Rev: 101608 DS26514 4-Port T1/E1/J1 Transceiver FRAMER #4 INTERFACE #4 FRAMER #3 INTERFACE ...

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Figure 7-2. Detailed Block Diagram TRANSCEIVER TRANSMIT TTIPn LIU Waveform Shaper/Line TRINGn Driver RECEIVE RTIPn LIU Clock/Data RRINGn Recovery MICROPROCESSOR INTERFACE Serial Interface Mode: SPI (SCLK, CPOL, CPHA, SWAP, MOSI, and MISO) Rev: 101608 DS26514 Tx BERT ...

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PIN DESCRIPTIONS 8.1 Pin Functional Description Table 8-1. Detailed Pin Descriptions NAME PIN TTIP1 A1, A2 TTIP2 H1, H2 TTIP3 J1 J2 TTIP4 T1, T2 Impedance TRING1 A3, B3 TRING2 G3, H3 TRING3 J3, K3 TRING4 R3, T3 Impedance ...

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NAME PIN TSER1 F6 TSER2 E7 TSER3 R4 TSER4 N7 TCLK1 C5 TCLK2 D7 TCLK3 P5 TCLK4 L8 TSYSCLK1 P13 TSYSCLK2/ F3 AL/RSIGF/FLOS2 TSYSCLK3/ L3 AL/RSIGF/FLOS3 TSYSCLK4/ Input with P3 AL/RSIGF/FLOS4 internal pulldown/ Output TSYNC1/ B4 TSSYNCIO1 TSYNC2/ F7 TSSYNCIO2 ...

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NAME PIN TSSYNCIO N13 Output TSIG1 D5 TSIG2 A6 TSIG3 T4 TSIG4 R6 TCHBLK1/ A5 TCHCLK1 TCHBLK2/ C7 TCHCLK2 TCHBLK3/ L7 TCHCLK3 TCHBLK4/ P7 TCHCLK4 Output Rev: 101608 TYPE Note: In default operation, this pin is not used. When GTCR1.528MD ...

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NAME PIN RSER1 E5 RSER2 D6 RSER3 N4 Output RSER4 N6 RCLK1 F4 RCLK2 G4 Output RCLK3 L4 RCLK4 M4 RSYSCLK1 L12 RSYSCLK2/ E3 RLF/LTC2 RSYSCLK3/ M3 RLF/LTC3 RSYSCLK4/ N3 Input with RLF/LTC4 internal pulldown/ Output RSYNC1 A4 RSYNC2 B6 ...

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NAME PIN RCHBLK1/ E4 RCHCLK1 RCHBLK2/ B5 RCHCLK2 RCHBLK3/ L6 RCHCLK3 RCHBLK4/ T5 RCHCLK4 Output BPCLK1 E8 Output CLKO/ D3 Output RLF/LTC1 A12 C8 A11 A8 A10 ...

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NAME PIN D[5]/SPI_SWAP M9 Output D[4] R8 Output D[3] T8 Output D[2]/SPI_SCLK P8 Output D[1]/SPI_MOSI L9 D[0]/SPI_MISO N8 Output CSB T7 RDB/ M8 DSB WRB/ R7 RWB Output, INTB R9 Stateable Input with SPI_SEL/ internal C3 AL/RSIGF/FLOS1 pulldown/ Output BTS ...

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NAME PIN RESETB J12 REFCLKIO A7 Output DIGIOEN D8 JTRST L5 JTMS K4 JTCLK F5 JTDI H4 Output, JTDO J4 Impedance SCANMODE H13 B1, B16, G1, G16, ATVDD K1, K16, R1, R16 B2, B15, G2, G15, ATVSS K2, K15, R2, ...

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NAME PIN G5, G6, G11, G12, DVDD33 H5, H6, H8, H9, H10, H11 DVDD18 G7–G10 H12, J6, J8–J11, DVSS K5–K12 Rev: 101608 TYPE 3.3V ±5% Power Supply for I/Os — 1.8V ±5% Power Supply for Internal V — Digital Ground ...

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FUNCTIONAL DESCRIPTION 9.1 Processor Interface Microprocessor control of the DS26514 is accomplished through the 28 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus ...

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SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing. Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI 1 A13 ...

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SPI_SCLK CSB 0 A13 A12 A11 A10 SPI_MOSI MSB SPI_MISO Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 SPI_SCLK CSB 0 A13 A12 A11 A10 SPI_MOSI MSB SPI_MISO Figure 9-7. SPI Serial Port ...

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Clock Structure The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz multiple the T1 and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy. ...

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CLKO Output Clock Generation This clock output is derived from MCLK based upon the setting of the CLKOSEL[2:0] bits in the register.The reference for the PLL is not the input clock on MCLK, but the scaled version of MCLK ...

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Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset ...

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Initialization and Configuration 9.4.1 Example Device Initialization and Sequence STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device using the software reset bits outlined in Section 9.3. Clear all reset ...

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Figure 9-10. Device Interrupt Information Flow Diagram Receive Remote Alarm Indication Clear Receive Alarm Condition Clear Receive Loss of Signal Clear Receive Loss of Frame Clear Receive Remote Alarm Indication Receive Alarm Condition Receive Loss of Signal Receive Loss of ...

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System Backplane Interface The DS26514 provides a versatile backplane interface that can be configured to: • Transmit and receive two-frame elastic stores • Mapping of T1 channels into a 2.048MHz backplane • IBO mode for multiple framers to share ...

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Elastic Stores Initialization There are two elastic store initializations that may be used to improve performance in certain applications: elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write ...

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Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit in TIOCR.4 enables the transmit elastic store to operate with a 2.048MHz backplane (32 time slots / frame). In this mode the user can choose which of ...

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Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user ...

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Figure 9-11. IBO Multiplexer Equivalent Circuit—4.096MHz Port # 1 Backplane Interface Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface Rev: 101608 RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB ...

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Figure 9-12. IBO Multiplexer Equivalent Circuit—8.192MHz DS26514 #1 Port # 1 Backplane Interface DS26514 #1 Port # 2 Backplane Interface DS26514 #1 Port # 3 Backplane Interface DS26514 #1 Port # 4 Backplane Interface Rev: 101608 RSER RSIG RIBO_OEB RSYNC ...

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Figure 9-13. IBO Multiplexer Equivalent Circuit—16.384MHz RSER RSIG DS26514 #1 RIBO_OEB Port # 1 RSYNC RSYSCLK Backplane Interface TSER TSIG TSSYNC TSYSCLK RSER RSIG DS26514 #1 RIBO_OEB Port # 2 RSYNC RSYSCLK Backplane Interface TSER TSIG TSSYNC TSYSCLK RSER RSIG ...

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Table 9-6. RSER Output Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE NAME Rx Serial Data for RSER1 Port # 1 Rx Serial Data for RSER2 Port # 2 Rx Serial Data for RSER3 Port # 3 Rx Serial Data ...

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Table 9-8. TSER Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE NAME Tx Serial Data for TSER1 Port # 1 Tx Serial Data for TSER2 Port # 2 Tx Serial Data for TSER3 Port # 3 Tx Serial Data ...

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Table 9-10. RSYNC Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE NAME Rx Frame Pulse for RSYNC1 port # 1 Rx Frame Pulse for RSYNC2 port # 2 Rx Frame Pulse for RSYNC3 port # 3 Rx Frame Pulse ...

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Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode 1 RSYNCn 2 RSYNCn RSYSCLKn BIT 8 RSERn NOTE 1: RSYNCn INPUT MODE IN NORMAL OPERATION. NOTE 2: RSYNCn INPUT MODE, H100EN = 1 AND RSYNCINV = 1. NOTE 3: t ...

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Transmit and Receive Channel Blocking Registers The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLKn and TCHBLKn pins, respectively. The RCHBLKn and TCHBLKn pins are user-programmable outputs that can be forced either ...

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Framers The DS26514 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms also used for extracting and inserting signaling data, ...

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Table 9-12. ESF Framing Mode FRAME FRAMING NUMBER Table 9-13. SLC-96 ...

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FRAME NUMBER ...

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E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 9-14. E1 FAS/NFAS Framing CRC-4 FRAME TYPE FAS C1 1 NFAS 0 2 FAS C2 3 NFAS 0 4 FAS C3 5 ...

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Table 9-15 shows the registers that are related to setting up the framing. Table 9-15. Registers Related to Setting Up the Framer REGISTER Transmit Master Mode Register (TMMR) Transmit Control Register 1 (TCR1) Transmit Control Register 2 (T1.TCR2) Transmit Control ...

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T1 Transmit Synchronizer The DS26514 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSERn. The TFM (TCR3.2) control bit determines whether the transmit synchronizer ...

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Signaling The DS26514 supports both software and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26514 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss or change of frame alignment. The ...

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Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit signaling registers, TS1–TS16, while hardware based refers to using the TSIGn pins. ...

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Receive-Signaling Operation There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit- and receive-signaling registers, RS1–RS16. Hardware based refers to the RSIGn ...

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Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment mode, this action ...

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Receive SLC-96 Operation (T1 Mode Only SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is ...

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T1 Data Link 9.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller The DS26514 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Table ...

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Legacy T1 Transmit FDL It is recommended that the DS26514’s built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. Table 9-21 shows the registers related to control of the transmit FDL. Table 9-21. ...

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E1 Data Link Table 9-23 shows the registers related to E1 data link. Table 9-23. Registers Related to E1 Data Link REGISTER E1 Receive Align Frame Register (E1RAF) E1 Receive Non-Align Frame Register Register (E1RNAF) E1 Received Si Bits ...

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Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26514, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal an ...

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Table 9-24 shows some of the registers related to maintenance and alarms. Table 9-24. Registers Related to Maintenance and Alarms REGISTER Receive Real-Time Status Register 1 (RRTS1) Receive Interrupt Mask Register 1(RIM1) Receive Latched Status Register 2 (RLS2) Receive Real-Time ...

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Status and Information Bit Operation When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. ...

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Alarms Table 9-25. T1 Alarm Criteria ALARM AIS (Blue Alarm) (See Note Bit 2 Mode (T1RCR2 12th F-Bit Mode (T1RCR2 (Note: This mode is also referred to as the RAI ...

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Receive RAI Table 9-27 shows the registers related to the receive RAI (Yellow Alarm). Table 9-27. Registers Related to Receive RAI (Yellow Alarm) REGISTER Receive Control Register 2 (T1RCR2.RRAIS) Receive Control Register 2 (T1RCR2.RAIIE) Note: The addresses shown above ...

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Error Count Registers The DS26514 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only) or manually. See ...

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Path Code Violation Count Register (PCVCR operation, the Path Code Violation Count Register records either Ft, Fs, or CRC-6 errors. When the receive side of a framer is set to operate in the T1 ESF framing mode, ...

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DS0 Monitoring Function The DS26514 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. Table 9-32 Table 9-32. Registers Related to DS0 Monitoring REGISTER Transmit DS0 ...

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Transmit Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Code Definition Registers (TIDR1–32) are provided to set the 8-bit idle code ...

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T1 Programmable In-Band Loop Code Generator The DS26514 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-33. Registers Related to ...

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T1 Programmable In-Band Loop Code Detection The DS26514 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-34. Registers Related to ...

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Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by RCR3. Table 9-35. Register Related to Framer Payload Loopbacks RECEIVE CONTROL FRAMER 1 REGISTER 3 (RCR3) ADDRESSES Framer Loopback Payload Loopback Remote Loopback Note: The addresses shown ...

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HDLC Controllers There are two HDLC Controllers available for each port of the DS26514. HDLC-64 is the default HDLC controller, which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is available on the DS26514 ...

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REGISTER (TLS2) Transmit Interrupt Mask Register 2 (TIM2) Transmit HDLC-64 FIFO Buffer Available (TFBA) Transmit HDLC-64 FIFO (THF) Note: The addresses shown are for Framer 1. Addresses for Framers can be calculated using the following: Framer n ...

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Receive HDLC-64 Example The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences. When receiving HDLC messages, the host can choose to be interrupt driven, to poll to desired status registers, or ...

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Transmit HDLC-64 Controller 9.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available Register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many ...

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Figure 9-18. HDLC Message Transmit Example Loop Action Required Work Another Process 9.10.3 HDLC-256 Controller This device has an enhanced HDLC controller that can be mapped into time slots, or Sa4 to Sa8 bits ...

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The HDLC-256 controller performs all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks ...

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If the Receive FIFO is read while the FIFO is empty, the read is ignored, and an invalid data indication given. The Transmit FIFO accepts data from the host until full. If the ...

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Figure 9-19. Receive HDLC Example Configure Receive HDLC-256 Controller (RH256CR1,2) Reset FIFO (RH256CR1.RFRST) Enable Interrupts (RHDAIE, RPEIE) INTB Active? YES Read RH256SRL RHDAL Set? YES Read RH256FDR1 8xRDAL - Read RH256FDR1, 2; ...

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Transmit HDLC-256 Example The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences. When transmitting HDLC messages, the host can choose to be interrupt driven poll to desired status registers, ...

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Figure 9-20. HDLC Message Transmit Example Configure Transmit HDLC-256 Controller (TH256CR1,2) Reset FIFO (TH256CR1.TFRST) Enable Interrupt INTB Active? Read TH256SRL THDAL Set? Write TH256FDR1 8xTDAL -1 Write TH256FDR1, 2; Packet End? Rev: 101608 (THDA) NO exit YES ...

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Power-Supply Decoupling Table 9-38. Recommended Supply Decoupling SUPPLY PINS DECOUPLING CAPACITANCE DVDD33 / DVSS 0.01μF + 0.1μF + 1μF + 10μF DVDDI8 / DVSS 0.01μF + 0.1μF + 1μF + 10μF ATVDD[4 :1] / 0.1μF (x4) + 1μF (x2) ...

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Line Interface Units (LIUs) The DS26514 has four identical LIU transmit and receive front-ends for each of the four framers. Each LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock ...

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Figure 9-21. Network Connection—Longitudinal Protection F1 TX TIP S7 TX RING TIP S8 RX RING F4 NAME DESCRIPTION 1.25A Slow Blow Fuse 1.25A Slow Blow Fuse S1, S2 25V (max) Transient Suppressor S3, S4, ...

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LIU Operation The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer coupled into the RTIPn and RRINGn pins of the DS26514. The user has the option to use ...

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Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator enabled for the transmit path. A digital sequencer and DAC ...

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Transmit-Line Pulse Shapes The DS26514 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in shape can be configured for each LIU on an individual basis. The ...

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Rev: 101608 194ns 219ns -200 -150 -100 - TIME (ns) DS26514 4-Port T1/E1/J1 Transceiver 269ns G.703 Template 100 150 200 250 90 ...

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Transmit G.703 Section 10 Synchronization Signal The DS26514 can transmit a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T G.703. To use this mode, set the transmit G.703 synchronization clock bit (TG703) found in the LIU ...

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RECEIVE LIU R T The device couples to the receive twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 or 2:1 transformer. See Table 9-41 for transformer details. Receive sensitivity is configurable by setting ...

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Figure 9-25. Typical Monitor Application T1/E1 LINE Rm 9.12.3.5 Loss of Signal The DS26514 uses both the digital and analog loss-detection method in compliance with the latest T1.231 for T1/J1 and ITU-T G.775 or ETS 300 233 for E1 mode ...

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Table 9-42. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications CRITERIA T1.231 No pulses are detected for 175 Loss ±75 bits. Detection Loss is terminated if a duration of 12.5% ones are detected over duration of 175 ±75 bits. ...

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Hitless Protection Switching (HPS) Many current redundancy protection implementations use mechanical relays to switch between primary and backup boards. The switching time in relays is typically in the milliseconds, making T1/E1 HPS impossible. The switching event will likely cause ...

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Jitter Attenuator Each LIU contains a jitter attenuator that can be set to a depth 128 bits via the JADS bits in LIU Transmit and Receive Control Register (LTRCR). The 128-bit mode is used in applications ...

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LIU Loopbacks The DS26514 provides four LIU loopbacks for diagnostic purposes: Analog Loopback, Local Loopback, Remote Loopback 1, and Remote Loopback 2. Dual Loopback is a combination of Local Loopback and Remote Loopback 1. In the loopback diagrams that ...

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Local Loopback The transmit system data is looped back to the receive framer. This data is also encoded and output on TTIPn and TRINGn. Signals at RTIPn and RRINGn are ignored. This loopback is conceptually shown in Figure 9-30. ...

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Dual Loopback The inputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are looped back to the receiver with the optional jitter attenuator. Dual Loopback is a combination of ...

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Bit Error-Rate Test Function (BERT) The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating bit patterns used to test and stress data-communication links. BERT functionality is dedicated for each of the ...

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BERT Status Interrupt Mask Register 2 (BLSR2) Note: The addresses shown above are for Framer 1. The BERT block can generate and detect the following patterns: • The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS. • A repetitive pattern ...

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DEVICE REGISTERS Thirteen address bits are used to control the settings of the registers. The registers control functions of the framers, LIUs, and BERTs within the DS26514. The map is divided into four framers, followed by four LIUs and ...

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Global Register List Table 10-2. Global Register List ADDRESS NAME 00F0h GTCR1 00F1h GFCR1 00F2h GTCR3 00F3h GTCCR1 00F4h GTCCR3 00F5h GHISR 00F6h GSRR1 00F7h GHIMR 00F8h IDR 00F9h GFISR1 00FAh GBISR1 00FBh GLISR1 00FCh GFIMR1 00FDh GBIMR1 00FEh ...

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Framer Register List Table 10-3. Framer Register List Note that only Framer 1 address is presented here. The same set of registers definitions applies for transceivers accordance with the DS26514 map offsets. Transceiver offset is ...

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ADDRESS NAME RIDR30 T1RDMWE3 03Eh RIDR31 03Fh RIDR32 040h RS1 041h RS2 042h RS3 043h RS4 044h RS5 045h RS6 046h RS7 047h RS8 048h RS9 049h RS10 04Ah RS11 04Bh RS12 04Ch RS13 04Dh RS14 04Eh RS15 04Fh RS16 ...

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ADDRESS NAME 080h RMMR RCR1 081h RCR1 T1RIBCC 082h E1RCR2 083h RCR3 084h RIOCR 085h RESCR 086h ERCNT 087h RHFC 088h RIBOC 089h T1RSCC 08Ah RXPC 08Bh RBPBS 08Ch - 08Dh RHBS 08Eh-08Fh - 090h RLS1 RLS2 091h RLS2 RLS3 ...

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ADDRESS NAME 0AFh T1RDNCD2 0B0h RRTS1 0B1h — RRTS3 0B2h RRTS3 0B3h — 0B4h RRTS5 0B5h RHPBA 0B6h RHF 0B7h–0BFh — 0C0h RBCS1 0C1h RBCS2 0C2h RBCS3 0C3h RBCS4 0C4h RCBR1 0C5h RCBR2 0C6h RCBR3 0C7h RCBR4 0C8h RSI1 0C9h ...

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ADDRESS NAME 10Ah TDDS3 110h THC1 111h THBSE 112h — 113h THC2 114h E1TSACR 115h–117h — 118h SSIE1 119h SSIE2 11Ah SSIE3 11Bh SSIE4 11Ch–11Fh — 120h TIDR1 121h TIDR2 122h TIDR3 123h TIDR4 124h TIDR5 125h TIDR6 126h TIDR7 ...

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ADDRESS NAME 149h TS10 14Ah TS11 14Bh TS12 14Ch TS13 14Dh TS14 14Eh TS15 14Fh TS16 150h TCICE1 151h TCICE2 152h TCICE3 153h TCICE4 154h–161h — 162h T1TFDL 163h T1TBOC T1TSLC1 164h E1TAF T1TSLC2 165h E1TNAF T1TSLC3 166h E1TSiAF 167h ...

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ADDRESS NAME 1A2h TIM3 1A3h–1ABh — 1ACh T1TCD1 1ADh T1TCD2 1AEh–1B0h — 1B1h TRTS2 1B2h — 1B3h TFBA 1B4h THF 1B5h–1BhA — 1BBh TDS0M 1BCh–1BFh — 1C0h TBCS1 1C1h TBCS2 1C2h TBCS3 1C3h TBCS4 1C4h TCBR1 1C5h TCBR2 1C6h TCBR3 ...

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LIU Register List Table 10-4. LIU Register List Note that only the LIU 1 address is presented here. The same set of registers definitions applies for LIUs accordance with the DS26514 map offsets. LIU offset ...

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BERT Register List Table 10-5. BERT Register List Note that only the BERT 1 address is presented here. The same set of registers definitions applies for BERTs accordance with the DS26514 map offsets. BERT offset ...

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HDLC-256 Register List Table 10-6. HDLC-256 Register List Note that only HDLC-256 1 Address is presented here. The same set of registers definitions applies for HDLC-256s accordance with the DS26514 map offsets. HDLC-256 offset is ...

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Register Bit Maps 10.2.1 Global Register Bit Map Table 10-7. Global Register Bit Map ADDR NAME BIT 7 00F0h GTCR1 GPSEL3 00F1h GFCR1 IBOMS1 00F2h GTCR3 — 00F3h GTCCR1 BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL FREQSEL 00F4h GTCCR3 RSYSCLKSEL TSYSCLKSEL ...

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Framer Register Bit Map Table 10-8 contains the framer registers of the DS26514. Some registers have dual functionality based on the selection of T1/ operating mode in the shown below using two lines of text. The first ...

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ADDR NAME BIT 7 RIDR25 C7 T1RSAOI2 CH16 039h RIDR26 C7 T1RSAOI3 CH24 03Ah RIDR27 C7 — 03Bh RIDR28 C7 T1RDMWE1 CH8 03Ch RIDR29 C7 T1RDMWE2 CH16 03Dh RIDR30 C7 T1RDMWE3 CH24 03Eh RIDR31 C7 — 03Fh RIDR32 C7 CH1-A ...

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ADDR NAME BIT 7 051h LCVCR2 LCVC7 052h PCVCR1 PCVC15 053h PCVCR2 PCVC7 054h FOSCR1 FOS15 055h FOSCR2 FOS7 056h E1EBCR1 EB15 057h E1EBCR2 EB7 058h FEACR1 FEACR15 059h FEACR2 FEACR7 05Ah FEBCR1 FEBCR15 05Bh FEBCR2 FEBCR7 060h RDS0M B1 ...

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ADDR NAME BIT 7 090h RLS1 RRAIC RLS2 (T1) — 091h RLS2 (E1) — RLS3 (T1) LORCC 092h RLS3 (E1) LORCC 093h RLS4 RESF 094h RLS5 — RLS7 (T1) — 096h RLS7 (E1) — 097h — — 098h RSS1 CH8 ...

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ADDR NAME BIT 7 0C2h RBCS3 CH24 — 0C3h RBCS4 CH32 0C4h RCBR1 CH8 0C5h RCBR2 CH16 0C6h RCBR3 CH24 — 0C7h RCBR4 CH32 0C8h RSI1 CH8 0C9h RSI2 CH16 0CAh RSI3 CH24 — 0CBh RSI4 CH32 0CCh RGCCS1 CH8 ...

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ADDR NAME BIT 7 11Ah SSIE3 CH24 — 11Bh SSIE4 CH32 120h TIDR1 C7 121h TIDR2 C7 122h TIDR3 C7 123h TIDR4 C7 124h TIDR5 C7 125h TIDR6 C7 126h TIDR7 C7 127h TIDR8 C7 128h TIDR9 C7 129h TIDR10 ...

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ADDR NAME BIT 7 CH3-A CH5-A 144h TS5 CH4-A CH6-A 145h TS6 CH5-A CH7-A 146h TS7 CH6-A CH8-A 147h TS8 CH7-A CH9-A 148h TS9 CH8-A CH10-A 149h TS10 CH9-A CH11-A 14Ah TS11 CH10-A CH12-A 14Bh TS12 CH11-A — 14Ch TS13 ...

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ADDR NAME BIT 7 TSa6F15 — 16Ch E1TSa7 TSa7F15 — 16Dh E1TSa8 TSa8F15 180h TMMR FRM_EN TCR1 (T1) TJC 181h TCR1 (E1) TTPT T1.TCR2 TFDLS (T1) 182h E1.TCR2 AEBE (E1) — 183h TCR3 — TCLKINV 184h TIOCR TCLKINV 185h TESCR ...

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ADDR NAME BIT 7 — 1C3h TBCS4 CH32 1C4h TCBR1 CH8 1C5h TCBR2 CH16 1C6h TCBR3 CH24 — 1C7h TCBR4 CH32 1C8h THSCS1 CH8 1C9h THSCS2 CH16 1CAh THSCS3 CH24 — 1CBh THSCS4 CH32 1CCh TGCCS1 CH8 1CDh TGCCS2 CH16 ...

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LIU Register Bit Map Table 10-10. LIU Register Bit Map ADDR NAME BIT 7 1000h LTRCR — 1001h LTIPSR TG703 TIMPTON 1002h LMCR TAIS 1003h LRSR — 1004h LSIMR JALTCIM 1005h LLSR JALTC 1006h LRSL RSL3 1007h LRISMR — ...

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BERT Register Bit Map Table 10-11. BERT Register Bit Map ADDR NAME BIT 7 1100h BAWC ACNT7 1101h BRP1 RPAT7 1102h BRP2 RPAT15 1103h BRP3 RPAT23 1104h BRP4 RPAT31 1105h BC1 TC 1106h BC2 EIB2 1107h BBC1 BBC7 1108h ...

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HDLC-256 Register Bit Map Table 10-12. HDLC-256 Register Bit Map ADDR NAME BIT 7 1500h TH256CR1 -- 1501h TH256CR2 -- 1502h TH256FDR1 -- 1503h TH256FDR2 TFD7 1504h TH256SR1 -- 1505h TH256SR2 -- 1506h TH256SRL -- 1507h -- -- 1508h ...

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Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK1 configuration. The global registers bit descriptions are presented below. Table 10-13. ...

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Register Name GTCR1 Register Description: Global Transceiver Control Register 1 Register Address: 00F0h Bit # 7 6 Name GPSEL3 GPSEL2 Default 0 0 Bits General-Purpose I/O Pins Select (GPSEL[3:1]) Table 10-14. Output Status Control GPSEL[3:1] RLF/LTC[4:1] 000 ...

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Register Name: GFCR1 Description: Global Framer Control Register 1 Register Address: 00F1h Bit # 7 6 Name IBOMS1 IBOMS0 Default 0 0 Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These bits determine the configuration ...

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Register Name: GTCR3 Register Description: Global Transceiver Control Register 3 Register Address: 00F2h Bit # 7 6 Name — — Default 0 0 Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL TSSYNCIO[4:1] are inputs on TSYNC/TSSYNCIO[4:1] pins 1 ...

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Register Name: GTCCR1 Register Description: Global Transceiver Clock Control Register 1 Register Address: 00F3h Bit # 7 6 Name BPREFSEL3 BPREFSEL2 Default 0 0 Bits Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select which reference clock source ...

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