STM32W108C8U63TR STMicroelectronics, STM32W108C8U63TR Datasheet - Page 111

• Manufacturer Part Number: STM32W108C8U63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108C8U63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (64 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108C8
reload value, whereas the prescalar's counter restarts from 0, but the prescale rate doesn't
change.
In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit
generates an update event, but without setting the INT_TIMUIF flag. Thus no interrupt
request is sent. This avoids generating both update and capture interrupts when clearing the
counter on the capture event.
When an update event occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG
register) is set (unless TIM_USR is 1) and the following registers are updated:
●
●
Figure 19
frequencies when TIMx_ARR = 0x36.
Figure 19. Counter timing diagram, internal clock divided by 1
Figure 20. Counter timing diagram, internal clock divided by 4
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (contents of the
TIMx_ARR register) - 1 and generates a counter overflow event, then counts from the
The prescaler shadow register is reloaded with the buffer value (contents of the
TIMx_PSC register).
The auto-reload active register is updated with the buffer value (contents of the
TIMx_ARR register). The auto-reload is updated before the counter is reloaded, so that
the next period is the expected one.
and
Figure 20
show some examples of the counter behavior for different clock
Doc ID 018587 Rev 1
General-purpose timers
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