AD5755-1ACPZ Analog Devices Inc, AD5755-1ACPZ Datasheet - Page 33

• Manufacturer Part Number: AD5755-1ACPZ
• Description: 16Bit Quad,V/I DAC No Dynamic Power Ctrl
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of AD5755-1ACPZ

• Input Channel Type: Serial
• Data Interface: 3-Wire, Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +105°C
• Rohs Compliant: Yes
• Resolution (bits): 16bit
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Featured Product: AD5755 / AD5755-1 / AD5757 DACs
• Settling Time: 11µs
• Number Of Bits: 16
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): -
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 64-VFQFN Exposed Pad, CSP
• Number Of Outputs And Type: 4 Current, 4 Voltage
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Gain Register
The 16-bit gain register, as shown in Table 11, allows the user to
adjust the gain of each channel in steps of 1 LSB. This is done by
setting the DREG[2:0] bits to 010. It is possible to write the
same gain code to all four DAC channels at the same time by
setting the DREG[2:0] bits to 011. The gain register coding is
straight binary as shown in Table 12. The default code in the
gain register is 0xFFFF. In theory, the gain can be tuned across
the full range of the output. In practice, the maximum
recommended gain trim is about 50% of programmed range to
maintain accuracy. See the Digital Offset and Gain Control
section for more information.
Offset Register
The 16-bit offset register, as shown in Table 13, allows the user to
adjust the offset of each channel by −32,768 LSBs to +32,767 LSBs
Table 11. Programming the Gain Register
R/W
0
Table 12. Gain Register
Gain Adjustment
+65,535 LSBs
+65,534 LSBs
…
1 LSB
0 LSBs
Table 13. Programming the Offset Register
R/W
0
Table 14. Offset Register Options
Offset Adjustment
+32,767 LSBs
+32,766 LSBs
…
No Adjustment (Default)
…
−32,767 LSBs
−32,768 LSBs
Table 15. Programming the Clear Code Register
R/W
0
DUT_AD1
DUT_AD1
DUT_AD1
Device address
Device address
Device address
DUT_AD0
DUT_AD0
DUT_AD0
…
…
OF15
1
1
1
0
0
DREG2
G15
1
1
…
0
0
OF14
1
1
…
0
…
0
0
0
DREG2
1
DREG2
1
DREG1
1
DREG1
0
OF13
1
1
…
0
…
0
0
G14
1
1
…
0
0
DREG1
1
Rev. A | Page 33 of 48
DREG0
0
G13
1
1
…
0
0
DREG0
0
OF12 to OF4
1
1
…
0
…
0
0
DREG0
0
in steps of 1 LSB. This is done by setting the DREG[2:0] bits to
100. It is possible to write the same offset code to all four DAC
channels at the same time by setting the DREG[2:0] bits to 101.
The offset register coding is straight binary as shown in Table 14.
The default code in the offset register is 0x8000, which results in
zero offset programmed to the output. See the Digital Offset
and Gain Control section for more information.
Clear Code Register
The 16-bit clear code register allows the user to set the clear
value of each channel as shown in Table 15. It is possible, via
software, to enable or disable on a per channel basis which
channels are cleared when the CLEAR pin is activated. The
default clear code is 0x0000. See the Asynchronous Clear
section for more information.
DAC_AD1
G12 to G4
1
1
…
0
0
DAC_AD1
DAC channel address
DAC channel address
OF3
1
1
…
0
…
0
0
DAC_AD1
DAC channel address
DAC_AD0
DAC_AD0
DAC_AD0
G3
1
1
…
0
0
OF2
1
1
…
0
…
0
0
G2
1
1
…
0
0
D15 to D0
Offset adjustment
D15 to D0
Gain adjustment
G1
1
0
…
0
0
OF1
1
0
…
0
…
0
0
D15 to D0
Clear code
AD5755-1
OF0
…
…
1
0
0
0
0
G0
1
0
…
1
0