MT47H32M16HR-187E:G Micron Technology Inc, MT47H32M16HR-187E:G Datasheet - Page 78
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT47H32M16HR-187E:G
Manufacturer Part Number
MT47H32M16HR-187E:G
Description
IC DDR2 SDRAM 512MBIT 84FBGA
Manufacturer
Micron Technology Inc
Series
-r
Datasheet
1.MT47H32M16HR-187EG.pdf
(132 pages)
Specifications of MT47H32M16HR-187E:G
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (32Mx16)
Speed
1.875ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
84-TFBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H32M16HR-187E:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Write Recovery
Power-Down Mode
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 76).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 63 (page 110).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing
nanoseconds) by
integer; WR (cycles) =
known operation or incompatibility with future versions may result.
Active power-down (PD) mode is defined by bit M12, as shown in Figure 34. PD mode
enables the user to determine the active power-down mode, which determines perform-
ance versus power savings. PD mode bit M12 does not apply to precharge PD mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I
power mode is defined in the DDR2 I
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
t
CK (in nanoseconds) and rounding up a noninteger value to the next
t
WR (ns)/
78
t
CK (ns). Reserved states should not be used as an un-
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Specifications and Conditions table.
512Mb: x4, x8, x16 DDR2 SDRAM
DD3P
Mode Register (MR)
© 2004 Micron Technology, Inc. All rights reserved.
normal and I
t
WR (in
DD3P
low-
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