MT47H32M16HR-187E:G Micron Technology Inc, MT47H32M16HR-187E:G Datasheet - Page 6

• Manufacturer Part Number: MT47H32M16HR-187E:G
• Description: IC DDR2 SDRAM 512MBIT 84FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H32M16HR-187E:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 1.875ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Lead Free Status / Rohs Status: Compliant

List of Figures
Figure 1: 512Mb DDR2 Part Numbers .............................................................................................................. 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 64 Meg x 8 Functional Block Diagram .............................................................................................. 13
Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 13
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 15
Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16 ................................................................................................ 18
Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................... 19
Figure 10: Example Temperature Test Point Location ..................................................................................... 22
Figure 11: Single-Ended Input Signal Levels ................................................................................................... 44
Figure 12: Differential Input Signal Levels ...................................................................................................... 45
Figure 13: Differential Output Signal Levels .................................................................................................... 47
Figure 14: Output Slew Rate Load .................................................................................................................. 48
Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 49
Figure 16: Full Strength Pull-Up Characteristics ............................................................................................. 50
Figure 17: Reduced Strength Pull-Down Characteristics ................................................................................. 51
Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 52
Figure 19: Input Clamp Characteristics .......................................................................................................... 53
Figure 20: Overshoot ..................................................................................................................................... 54
Figure 21: Undershoot .................................................................................................................................. 54
Figure 22: Nominal Slew Rate for
Figure 23: Tangent Line for
Figure 24: Nominal Slew Rate for
Figure 25: Tangent Line for
Figure 26: Nominal Slew Rate for
Figure 27: Tangent Line for
Figure 28: Nominal Slew Rate for
Figure 29: Tangent Line for
Figure 30: AC Input Test Signal Waveform Command/Address Balls ............................................................... 67
Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 67
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 68
Figure 33: AC Input Test Signal Waveform (Differential) ................................................................................. 68
Figure 34: MR Definition ............................................................................................................................... 76
Figure 35: CL ................................................................................................................................................ 79
Figure 36: EMR Definition ............................................................................................................................. 80
Figure 37: READ Latency ............................................................................................................................... 83
Figure 38: WRITE Latency ............................................................................................................................. 83
Figure 39: EMR2 Definition ........................................................................................................................... 84
Figure 40: EMR3 Definition ........................................................................................................................... 85
Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 86
Figure 42: Example: Meeting
Figure 43: Multibank Activate Restriction ....................................................................................................... 90
Figure 44: READ Latency ............................................................................................................................... 92
Figure 45: Consecutive READ Bursts .............................................................................................................. 93
Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 94
Figure 47: READ Interrupted by READ ........................................................................................................... 95
Figure 48: READ-to-WRITE ............................................................................................................................ 95
Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 96
Figure 50: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 96
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
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IH ...................................................................................................................... 60
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DH ..................................................................................................................... 66
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RRD (MIN) and
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RCD (MIN) .............................................................................. 89
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.
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