PEF24911HV22XP Lantiq, PEF24911HV22XP Datasheet - Page 53
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PEF24911HV22XP
Manufacturer Part Number
PEF24911HV22XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF24911HV22XP.pdf
(155 pages)
Specifications of PEF24911HV22XP
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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3.8.2
Figure 21
M6 bit data:
Via the M4WMASK register the user can selectively program which M4 bits are
externally controlled and which are set by the internal state machine. If one M4WMASK
bit is set to ’0’ then the M4 bit value in the U-transmit frame is determined by the bit value
at the corresponding bit position of the MON-2 command.
Note that the MON-8 command PACE/PACA corresponds to bit 6 in the M4WMASK
register. By bit 6 it can be selected whether SAI is set by the state machine or by MON-
2 commands.
Note: During Local Loop test mode (C/I-input = ’ARL’), the user must neither send MON-
Via the M4RMASK register the user can selectively program which M4 bit changes shall
cause a MON-2 message. With respect to the SAI bit the corresponding bit (no. 6) in the
M4RMASK bit decides in addition whether the value of the received SAI bit is reported
to the state machine or SAI= ’1’ is signalled.
Access to M4WMASK and M4RMASK is provided by the MON-12 protocol. By MON-2
commands the M4 bits can be set that are sent with the next available U-superframe. By
MON-2 messages the status of the last validated M4 bit data is reported.
Also the default values of the spare bits, M51, M52 and M61 can be overwritten at any
time by a MON-2 command. A MON-2 messages reports the last received and verified
M5, M6 bit data.
Data Sheet
8 PACE/PACA, nor program register M4WMASK. Otherwise, switching back and
forth between PACE/PACA will easily cause a failure where the SAI/UOA bits
toggle permanently.
to
M4, M5, M6 Bit Control Mechanisms
Figure 22
show the control mechanisms that are provided for M4, M5 and
43
Functional Description
PEF 24911
2001-07-16
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