PEF24911HV22XP Lantiq, PEF24911HV22XP Datasheet - Page 42
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PEF24911HV22XP
Manufacturer Part Number
PEF24911HV22XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF24911HV22XP.pdf
(155 pages)
Specifications of PEF24911HV22XP
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Table 5
The data on SDR is interpreted as follows:
LD:
SY:
Data Sheet
2B1Q Data
+ 3
+ 1
– 3
– 1
0
First bit of the time-slots with transmission data. For synchronization and
The level detect information is communicated to the DFE-Q V2.1 on SDR.
If the signal amplitude reaches the wake-up level, the LD bit toggles with
the signal frequency. If the input signal at the U-interface is below the
wake-up level, the LD bit is tied to either low or high.
bit allocation on SDX, SY is set to ’1’ on SDX and ’0’ on SDR.
2B1Q Coding Table
TD2
1
0
0
0
0
32
don´t care
TD1
0
0
1
1
Functional Description
don´t care
TD0
PEF 24911
0
1
0
1
2001-07-16
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