PSB21150FV14NP Infineon Technologies, PSB21150FV14NP Datasheet - Page 66
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PSB21150FV14NP
Manufacturer Part Number
PSB21150FV14NP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21150FV14NP.pdf
(270 pages)
Specifications of PSB21150FV14NP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPU-
bit in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
3.3.10
The layer-1 part of the IPAC-X can be enabled/disabled by configuration (see
with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX .
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the IPAC-X does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The HDLC controller can still operate via IOM-2. The
DCL and FSC pins become input.
Figure 35
3.3.11
The IPAC-X provides test and diagnostic functions for the S/T interface:
Note: For more details please refer to the application note “Test Function of new S-
– The internal local loop (internal Loop A) is activated by a C/I command ARL or by
Data Sheet
setting the bit LP_A (Loop Analog) in the TR_CMD register if the layer-1 statemachine
Transceiver family”
Test Functions
Transceiver Enable/Disable
Disabling of S/T Transmitter
TR_CONF0.DIS_TR
TR_CONF2.DIS_TX
66
’1’
’0’
Description of Functional Blocks
PSB/PSF 21150
Figure
2003-01-30
IPAC-X
35)
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