PSB21150FV14NP Infineon Technologies, PSB21150FV14NP Datasheet - Page 234
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PSB21150FV14NP
Manufacturer Part Number
PSB21150FV14NP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21150FV14NP.pdf
(270 pages)
Specifications of PSB21150FV14NP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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RAL2
RSTAB
RAL1 ... Receive Address Byte Low Register 1
The general function (READ/WRITE) and the meaning or contents of this register
depends on the selected operating mode:
– Non-auto mode (16-bit address):
– Non-auto mode (8-bit address):
4.6.12
Value after reset: 00
RAL2 ... Receive Address Byte Low Register 2
Value of the second individual programmable low address byte. If a one byte address
field is selected, RAL2 is recognized as RESPONSE according to X.25 LAPB protocol.
4.6.13
Value after reset: 0E
VFR... Valid Frame
Determines whether a valid frame has been received.
The frame is valid (1) or invalid (0).
A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag,
abort).
RDO ... Receive Data Overflow
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in
RFIFOB. As opposed to ISTAB.RFO an RDO indicates that the beginning of a frame has
been received but not all bytes could be stored as the RFIFOB was temporarily full.
Data Sheet
RAL1 can be programmed with the value of the first individual low address byte.
According to X.25 LAPB protocol, the address in RAL1 is recognized as COMMAND
address.
7
7
RAL2 - RAL2 Register
RSTAB - Receive Status Register B-Channels
VFR
RDO
H
H
CRC
RAB
RAL2
234
HA1
HA0
Detailed Register Description
C/R
0
0
LA
PSB/PSF 21150
WR (78/88)
RD (78/88)
2003-01-30
IPAC-X
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