PSB21150FV14NP Infineon Technologies, PSB21150FV14NP Datasheet - Page 48

• Manufacturer Part Number: PSB21150FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3.3
The layer-1 functions for the S/T interface of the IPAC-X are:
– Line transceiver functions for the S/T interface according to the electrical
– Conversion of the frame structure between IOM-2 and S/T interface;
– Conversion from/to binary to/from pseudo-ternary code;
– Level detection
– Receive timing recovery for point-topoint, passive bus and extended passive bus
– S/T timing generation using IOM-2 timing synchronous to system, or vice versa;
– D-channel access control and priority handling;
– D-channel echo bit generation by handling of the global echo bit;
– Activation/deactivation procedures, triggered by primitives received over the IOM-2
– Execution of test loops.
The wiring configurations in user premises, in which the IPAC-X can be used, are
illustrated in
Data Sheet
specifications of ITU-T I.430;
configuration
C/I channel or by INFO's received from the line;
S/T-Interface
Figure
18.
48
Description of Functional Blocks
PSB/PSF 21150
2003-01-30
IPAC-X