PEB3086FV14NP Lantiq, PEB3086FV14NP Datasheet - Page 78
PEB3086FV14NP
Manufacturer Part Number
PEB3086FV14NP
Description
Manufacturer
Lantiq
Datasheet
1.PEB3086FV14NP.pdf
(262 pages)
Specifications of PEB3086FV14NP
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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Indication
Deactivation Request
from F6
Power up
Activation request
Activation request loop ARL
Illegal Code Violation
Activation indication
loop
Activation indication
with priority class 8
Activation indication
with priority class 10
Deactivation
confirmation
Data Sheet
Abbr. Code Remark
DR6
PU
AR
CVR
AIL
AI8
AI10
DC
0111 IOM-2 interface clocking is provided
0101 Deactivation Request from state F6
1000 Info 2 received
1010 Internal or external loop A closed
1011 Illegal code violation received. This function
1110 Internal or external loop A activated
1100 Info 4 received,
1101 Info 4 received,
1111 Clocks are disabled if CFS bit of register
has to be enabled by setting the EN_ICV bit of
register TR_CONF0.
D-channel priority is 8 or 9.
D-channel priority is 10 or 11.
MODE1 is set to ’1’, quiescent state
78
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX
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