PEB3086FV14NP Lantiq, PEB3086FV14NP Datasheet - Page 111
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PEB3086FV14NP
Manufacturer Part Number
PEB3086FV14NP
Description
Manufacturer
Lantiq
Datasheet
1.PEB3086FV14NP.pdf
(262 pages)
Specifications of PEB3086FV14NP
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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• As a slave device the transceiver part of the ISAC-SX is programmed and controlled
• For data exchange between two microcontroller systems attached to two different
3.7.3.1
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the MONITOR Channel Receive (MR) and MONITOR Channel
Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is
activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
The MONITOR channel protocol is described in the following section and
illustrates this. The relevant control and status bits for transmission and reception are
listed in
Table 12
Control/
Status Bit
Control
Status
Table 13
Control/
Status Bit
Control
Data Sheet
Status
from a master device on IOM-2 (e.g. ISAR 34 PSB 7115). This is used in applications
where no microcontroller is connected directly to the ISAC-SX in order to simplify host
interface connection. The HDLC controlling is processed by the master device
therefore the HDLC data is transferred via IOM-2 interface directly to the master
device.
devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity
of a dedicated serial communication path between the two systems. This simplifies the
system design of terminal equipment.
Table 12
Handshake Procedure
MOSR
MOSR
Register
MOCR
MSTA
Register
MOCR
Transmit Direction
Receive Direction
and
Table
Bit
MXC
MIE
MDA
MAB
MAC
Bit
MRC
MRE
MDR
MER
13.
Function
Transmit Interrupt Enable
Data Acknowledged
Data Abort
Transmission Active
Function
MR Bit Control
Receive Interrupt Enable
Data Received
End of Reception
MX Bit Control
111
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX
Figure 59
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