PEB3086FV14NP Lantiq, PEB3086FV14NP Datasheet - Page 11
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PEB3086FV14NP
Manufacturer Part Number
PEB3086FV14NP
Description
Manufacturer
Lantiq
Datasheet
1.PEB3086FV14NP.pdf
(262 pages)
Specifications of PEB3086FV14NP
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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List of Figures
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Figure 83
Figure 84
Figure 85
Figure 86
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Figure 88
Figure 89
Figure 90
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Figure 92
Figure 93
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Figure 95
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Figure 98
Data Sheet
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Interrupt Status Registers of the HDLC Controllers . . . . . . . . . . . . . . 153
Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Register Mapping of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 233
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
IOM-2 Timing (LT-S, LT-T, NT mode) . . . . . . . . . . . . . . . . . . . . . . . . 235
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 236
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Sampling Time in LT-S/NT Mode (M-Bit Input) . . . . . . . . . . . . . . . . . 242
Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Transformer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
11
PEB 3086
2003-01-30
ISAC-SX
Page
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