PEB24901HV1.2 Lantiq, PEB24901HV1.2 Datasheet - Page 56

• Manufacturer Part Number: PEB24901HV1.2
• Manufacturer: Lantiq

Specifications of PEB24901HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Frame jump
IOM awaked
Maintenance state
Power down
Sending awake-ack
Synchronized
Semiconductor Group
In the transmit or in the receive data buffer a data over- or
underflow has occurred. This is indicated to the associated
layer 2 device with code FJ for 0.5 ms (4 IOM-2 frames). The
RDS counter and the adaption of receiver coefficients are
enabled.
The LT in the exchange has received INFO U3 indicating that
the link is synchronized from and to the TE. The LT commands,
with 1 ms INFO U4H, the whole link to the TE to be switched
transparent. The RDS counter and the adaption of receiver
coefficients are enabled. If in 64 subsequent Uk0 frames the
Barker-code is not found at the expected position, the IECQuad
DFE-T gives out RSYD or RSYU on the C/I-channel until it has
resynchronized finding the Barker-code on the same position in
4 subsequent frames.
With SSP or LTD in the C/I-channel or with a low on pin RES
as well as a high on pin TSP, the Quad IEC DFE-T goes to the
maintenance state. The user data (B + B + D) on pin DOUT is
clamped to high.
If pins TSP and RES are high or code SSP is in the C/I-channel
input, the Quad IEC DFE-T sends each ms a single pulse on
the line to enable the test whether it fits into the specified pulse
mask.
IF pins RES and TSP are low or RES is in the C/I-channel
input, the Quad IEC DFE-T is reset in this state erasing all
stored coefficients. The Quad IEC DFE-T leaves the
maintenance state only if TSP is low, RES is high and code DR
or ARL is in the C/I-channel.
Entering this state, the Quad IEC DFE-T powers down within
0.5 ms stopping most parts of the Quad IEC DFE-T, so that
these CMOS circuits cannot consume further energy. The IOM-
2 interface units remain active as long as they are clocked via
CL15 pin, and the user data (B + B + D) on pin DOUT is
clamped to high .
The Quad IEC DFE-T has received the awake signal and
acknowledges this in this state. The user data (B + B + D) on
pin DOUT is clamped to high.
The LT-RP has recognized INFO U1 or U3, so 1,152
subsequent bits have been transferred without any bit error.
This indicates synchronization. Now the Quad IEC DFE-T itself
is ready to go to the transparent state.
55
PEB 24901
02.95