PEB24901HV1.2 Lantiq, PEB24901HV1.2 Datasheet - Page 27

• Manufacturer Part Number: PEB24901HV1.2
• Manufacturer: Lantiq

Specifications of PEB24901HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
SY:
LD:
Table 6
Assignments of Time-Slots on SDX/SDR to Line Ports
The assignment of the channels 0 to 3 to the time slots on SDX is given in table 5.The
4B3T data is coded with the bits TD1 and TD0. The Quad IEC AFE will transmit the
ternary pulses according to table 6.
Table 7
Coding of the 4B3T transmit pulse
3.2.3 Boundary Scan Test Controller
The Quad IEC DFE-T provides a boundary scan support for a cost effective board
testing. It consists of:
Time-Slot No.
– Complete boundary scan for 46 signals (pins) according to IEEE Std. 1149.1
– Test access port controller (TAP)
– Four dedicated pins (TCK, TMS, TDI, TDO)
– One 32-bit IDCODE register
– additional test command performing "send single pulses" mode
4B3T Data Pulse
specification
+ 1
– 1
First bit of the time slots with transmission data. For synchronisation and bit
allocation on SDX,SY is set to ONE on SDX and set to ZERO on SDR.
The Level-Detect bit indicates an analog signal being recognized at the line
inputs of the AFE. The DFE-T will evaluate whether this signal is the wake-up
signal "TN". LD being constantly tied to either ONE or ZERO indicates "no
signal on U". LD changes from ONE to ZERO with the period of the signal
detected by the AFE.
0
1
3
5
7
Line Port No.
TD1
0
1
1
0
1
2
3
26
TD0
0
1
0
PEB 24901
02.95