PSB21384HV13XT Infineon Technologies, PSB21384HV13XT Datasheet - Page 207
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PSB21384HV13XT
Manufacturer Part Number
PSB21384HV13XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21384HV13XT.pdf
(270 pages)
Specifications of PSB21384HV13XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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7.2
7.2.1
Value after reset: 01
TR_
CONF0
DIS_TR
0: All layer-1 functions are enabled
1: All layer-1 functions are disabled. All other functional blocks of the SCOUT can still
EN_FECV
0: normal operation
1: Far-end-code-violation (FECV) function according to ANSI T1.605 enabled. The
L1SW
0: Layer-1 statemachine of the SCOUT is used
1: Layer-1 statemachine is disabled. The functionality can be realized in software. The
EXLP
If the local loop is activated with the C/I command ARL or with the LP_A bit of the
TR_CMD register the loop is an
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/2
Note: The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
Data Sheet
operate via IOM-2. DCL and FSC pins become input
receipt of at least one illegal code violation within one multi-frame is indicated by the
C/I indication ’1011’ (CVR) in two consecutive IOM frames
commands can be written into the register TR_CMD and the status read from the
register TR_STA
Transceiver, Interrupt and General Configuration Registers
TR_CONF0 - Transceiver Configuration Register
7
DIS_
TR
... Disable Transceiver
... Enable Far-End-Code-Violation
... Enable Layer 1 State Machine in Software
... External Loop
H
0
FECV
EN_
0
197
L1SW
0
Detailed Register Description
EXLP
0
LDD RD/WR (30
PSB 21381/2
PSB 21383/4
2001-03-12
H
)
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