PSB21384HV13XT Infineon Technologies, PSB21384HV13XT Datasheet - Page 199
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PSB21384HV13XT
Manufacturer Part Number
PSB21384HV13XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21384HV13XT.pdf
(270 pages)
Specifications of PSB21384HV13XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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7.1.11
Value after reset: 00
RBCL
RBC7-0
Eight least significant bits of the total number of bytes in a received message.
7.1.12
Value after reset: FC
SAP2
SAPI2
Value of the second programmable Service Access Point Identifier (SAPI) according to
the ISDN LAPD-protocol.
MLA
0:
1:
7.1.13
Value after reset: 00
RBCH
OV
A ’1’ in this bit position indicates a message longer than (2
Data Sheet
The TEI address of an incoming frame is compared with TEI1, TEI2, TEIG
The TEI address of an incoming frame is compared with TEI1 and TEIG.
TEI1 can be masked with TEI2 thereby bit positions of TEI1 are not compared
if they are set to ’1’ in TEI2
RBCL - Receive Frame Byte Count Low
SAP2 - SAPI2 Register
RBCH - Receive Frame Byte Count High
RBC7
7
7
7
0
... Receive Byte Count
... SAPI2 value
... Mask Low Address
... Overflow
H
H
H
.
0
0
SAPI2
OV
RBC11
189
Detailed Register Description
12
- 1) = 4095 bytes .
0
0
0
0
RBC0
RBC8
MLA
PSB 21381/2
PSB 21383/4
2001-03-12
WR (26
RD (26
RD (27
H
H
H
)
)
)
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